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Add TargetInstrInfo::isSafeToMoveRegisterClassDefs. It returns true if it's safe to move an instruction which defines a value in the register class. Replace pre-splitting specific IgnoreRegisterClassBarriers with this new hook.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63936 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -427,10 +427,9 @@ public:
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return false;
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return false;
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}
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}
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/// IgnoreRegisterClassBarriers - Returns true if pre-register allocation
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/// isSafeToMoveRegClassDefs - Return true if it's safe to move a machine
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/// live interval splitting pass should ignore barriers of the specified
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/// instruction that defines the specified register class.
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/// register class.
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virtual bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
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virtual bool IgnoreRegisterClassBarriers(const TargetRegisterClass *RC) const{
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return true;
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return true;
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}
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}
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@ -1128,7 +1128,10 @@ PreAllocSplitting::SplitRegLiveIntervals(const TargetRegisterClass **RCs,
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// by the current barrier.
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// by the current barrier.
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SmallVector<LiveInterval*, 8> Intervals;
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SmallVector<LiveInterval*, 8> Intervals;
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for (const TargetRegisterClass **RC = RCs; *RC; ++RC) {
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for (const TargetRegisterClass **RC = RCs; *RC; ++RC) {
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if (TII->IgnoreRegisterClassBarriers(*RC))
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// FIXME: If it's not safe to move any instruction that defines the barrier
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// register class, then it means there are some special dependencies which
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// codegen is not modelling. Ignore these barriers for now.
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if (!TII->isSafeToMoveRegClassDefs(*RC))
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continue;
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continue;
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std::vector<unsigned> &VRs = MRI->getRegClassVirtRegs(*RC);
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std::vector<unsigned> &VRs = MRI->getRegClassVirtRegs(*RC);
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for (unsigned i = 0, e = VRs.size(); i != e; ++i) {
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for (unsigned i = 0, e = VRs.size(); i != e; ++i) {
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@ -2483,11 +2483,11 @@ ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
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}
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}
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bool X86InstrInfo::
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bool X86InstrInfo::
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IgnoreRegisterClassBarriers(const TargetRegisterClass *RC) const {
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isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
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// FIXME: Ignore bariers of x87 stack registers for now. We can't
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// FIXME: Return false for x87 stack register classes for now. We can't
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// allow any loads of these registers before FpGet_ST0_80.
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// allow any loads of these registers before FpGet_ST0_80.
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return RC == &X86::CCRRegClass || RC == &X86::RFP32RegClass ||
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return !(RC == &X86::CCRRegClass || RC == &X86::RFP32RegClass ||
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RC == &X86::RFP64RegClass || RC == &X86::RFP80RegClass;
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RC == &X86::RFP64RegClass || RC == &X86::RFP80RegClass);
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}
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}
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const TargetRegisterClass *X86InstrInfo::getPointerRegClass() const {
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const TargetRegisterClass *X86InstrInfo::getPointerRegClass() const {
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@ -406,10 +406,9 @@ public:
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virtual
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virtual
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bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
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bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
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/// IgnoreRegisterClassBarriers - Returns true if pre-register allocation
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/// isSafeToMoveRegClassDefs - Return true if it's safe to move a machine
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/// live interval splitting pass should ignore barriers of the specified
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/// instruction that defines the specified register class.
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/// register class.
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bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const;
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bool IgnoreRegisterClassBarriers(const TargetRegisterClass *RC) const;
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const TargetRegisterClass *getPointerRegClass() const;
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const TargetRegisterClass *getPointerRegClass() const;
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