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Change the interface to PromoteMemToReg to also take a DominatorTree

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@8883 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2003-10-05 21:20:13 +00:00
parent 5b15deedc0
commit 43f820d1f7
5 changed files with 17 additions and 6 deletions
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4
include/llvm/Transforms/Utils/PromoteMemToReg.h
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@ -9,6 +9,7 @@
#define TRANSFORMS_UTILS_PROMOTEMEMTOREG_H
class AllocaInst;
class DominatorTree;
class DominanceFrontier;
class TargetData;
#include <vector>
@ -24,6 +25,7 @@ bool isAllocaPromotable(const AllocaInst *AI, const TargetData &TD);
/// of the function at all. All allocas must be from the same function.
///
void PromoteMemToReg(const std::vector<AllocaInst*> &Allocas,
DominanceFrontier &DF, const TargetData &TD);
DominatorTree &DT, DominanceFrontier &DF,
const TargetData &TD);
#endif

5
lib/Transforms/Scalar/LICM.cpp
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@ -63,6 +63,7 @@ namespace {
private:
LoopInfo *LI; // Current LoopInfo
AliasAnalysis *AA; // Current AliasAnalysis information
DominanceFrontier *DF; // Current Dominance Frontier
bool Changed; // Set to true when we change anything.
BasicBlock *Preheader; // The preheader block of the current loop...
Loop *CurLoop; // The current loop we are working on...
@ -173,6 +174,7 @@ bool LICM::runOnFunction(Function &) {
// Get our Loop and Alias Analysis information...
LI = &getAnalysis<LoopInfo>();
AA = &getAnalysis<AliasAnalysis>();
DF = &getAnalysis<DominanceFrontier>();
DT = &getAnalysis<DominatorTree>();
// Hoist expressions out of all of the top-level loops.
@ -405,8 +407,7 @@ void LICM::PromoteValuesInLoop() {
PromotedAllocas.reserve(PromotedValues.size());
for (unsigned i = 0, e = PromotedValues.size(); i != e; ++i)
PromotedAllocas.push_back(PromotedValues[i].first);
PromoteMemToReg(PromotedAllocas, getAnalysis<DominanceFrontier>(),
AA->getTargetData());
PromoteMemToReg(PromotedAllocas, *DT, *DF, AA->getTargetData());
}
/// findPromotableValuesInLoop - Check the current loop for stores to definite

5
lib/Transforms/Scalar/ScalarReplAggregates.cpp
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@ -38,6 +38,7 @@ namespace {
// getAnalysisUsage - This pass does not require any passes, but we know it
// will not alter the CFG, so say so.
virtual void getAnalysisUsage(AnalysisUsage &AU) const {
AU.addRequired<DominatorTree>();
AU.addRequired<DominanceFrontier>();
AU.addRequired<TargetData>();
AU.setPreservesCFG();
@ -74,6 +75,8 @@ bool SROA::runOnFunction(Function &F) {
bool SROA::performPromotion(Function &F) {
std::vector<AllocaInst*> Allocas;
const TargetData &TD = getAnalysis<TargetData>();
DominatorTree &DT = getAnalysis<DominatorTree>();
DominanceFrontier &DF = getAnalysis<DominanceFrontier>();
BasicBlock &BB = F.getEntryBlock(); // Get the entry node for the function
@ -91,7 +94,7 @@ bool SROA::performPromotion(Function &F) {
if (Allocas.empty()) break;
PromoteMemToReg(Allocas, getAnalysis<DominanceFrontier>(), TD);
PromoteMemToReg(Allocas, DT, DF, TD);
NumPromoted += Allocas.size();
Changed = true;
}

6
lib/Transforms/Utils/Mem2Reg.cpp
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@ -25,6 +25,7 @@ namespace {
// getAnalysisUsage - We need dominance frontiers
//
virtual void getAnalysisUsage(AnalysisUsage &AU) const {
AU.addRequired<DominatorTree>();
AU.addRequired<DominanceFrontier>();
AU.addRequired<TargetData>();
AU.setPreservesCFG();
@ -41,6 +42,9 @@ bool PromotePass::runOnFunction(Function &F) {
BasicBlock &BB = F.getEntryBlock(); // Get the entry node for the function
bool Changed = false;
DominatorTree &DT = getAnalysis<DominatorTree>();
DominanceFrontier &DF = getAnalysis<DominanceFrontier>();
while (1) {
Allocas.clear();
@ -54,7 +58,7 @@ bool PromotePass::runOnFunction(Function &F) {
if (Allocas.empty()) break;
PromoteMemToReg(Allocas, getAnalysis<DominanceFrontier>(), TD);
PromoteMemToReg(Allocas, DT, DF, TD);
NumPromoted += Allocas.size();
Changed = true;
}

3
lib/Transforms/Utils/PromoteMemoryToRegister.cpp
View File

@ -361,7 +361,8 @@ void PromoteMem2Reg::RenamePass(BasicBlock *BB, BasicBlock *Pred,
/// of the function at all. All allocas must be from the same function.
///
void PromoteMemToReg(const std::vector<AllocaInst*> &Allocas,
DominanceFrontier &DF, const TargetData &TD) {
DominatorTree &DT, DominanceFrontier &DF,
const TargetData &TD) {
// If there is nothing to do, bail out...
if (Allocas.empty()) return;
PromoteMem2Reg(Allocas, DF, TD).run();