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Change the interface to PromoteMemToReg to also take a DominatorTree
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@8883 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -9,6 +9,7 @@
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#define TRANSFORMS_UTILS_PROMOTEMEMTOREG_H
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class AllocaInst;
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class DominatorTree;
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class DominanceFrontier;
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class TargetData;
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#include <vector>
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@ -24,6 +25,7 @@ bool isAllocaPromotable(const AllocaInst *AI, const TargetData &TD);
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/// of the function at all. All allocas must be from the same function.
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///
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void PromoteMemToReg(const std::vector<AllocaInst*> &Allocas,
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DominanceFrontier &DF, const TargetData &TD);
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DominatorTree &DT, DominanceFrontier &DF,
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const TargetData &TD);
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#endif
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@ -63,6 +63,7 @@ namespace {
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private:
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LoopInfo *LI; // Current LoopInfo
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AliasAnalysis *AA; // Current AliasAnalysis information
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DominanceFrontier *DF; // Current Dominance Frontier
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bool Changed; // Set to true when we change anything.
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BasicBlock *Preheader; // The preheader block of the current loop...
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Loop *CurLoop; // The current loop we are working on...
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@ -173,6 +174,7 @@ bool LICM::runOnFunction(Function &) {
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// Get our Loop and Alias Analysis information...
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LI = &getAnalysis<LoopInfo>();
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AA = &getAnalysis<AliasAnalysis>();
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DF = &getAnalysis<DominanceFrontier>();
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DT = &getAnalysis<DominatorTree>();
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// Hoist expressions out of all of the top-level loops.
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@ -405,8 +407,7 @@ void LICM::PromoteValuesInLoop() {
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PromotedAllocas.reserve(PromotedValues.size());
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for (unsigned i = 0, e = PromotedValues.size(); i != e; ++i)
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PromotedAllocas.push_back(PromotedValues[i].first);
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PromoteMemToReg(PromotedAllocas, getAnalysis<DominanceFrontier>(),
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AA->getTargetData());
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PromoteMemToReg(PromotedAllocas, *DT, *DF, AA->getTargetData());
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}
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/// findPromotableValuesInLoop - Check the current loop for stores to definite
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@ -38,6 +38,7 @@ namespace {
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// getAnalysisUsage - This pass does not require any passes, but we know it
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// will not alter the CFG, so say so.
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virtual void getAnalysisUsage(AnalysisUsage &AU) const {
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AU.addRequired<DominatorTree>();
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AU.addRequired<DominanceFrontier>();
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AU.addRequired<TargetData>();
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AU.setPreservesCFG();
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@ -74,6 +75,8 @@ bool SROA::runOnFunction(Function &F) {
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bool SROA::performPromotion(Function &F) {
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std::vector<AllocaInst*> Allocas;
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const TargetData &TD = getAnalysis<TargetData>();
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DominatorTree &DT = getAnalysis<DominatorTree>();
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DominanceFrontier &DF = getAnalysis<DominanceFrontier>();
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BasicBlock &BB = F.getEntryBlock(); // Get the entry node for the function
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@ -91,7 +94,7 @@ bool SROA::performPromotion(Function &F) {
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if (Allocas.empty()) break;
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PromoteMemToReg(Allocas, getAnalysis<DominanceFrontier>(), TD);
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PromoteMemToReg(Allocas, DT, DF, TD);
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NumPromoted += Allocas.size();
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Changed = true;
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}
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@ -25,6 +25,7 @@ namespace {
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// getAnalysisUsage - We need dominance frontiers
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//
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virtual void getAnalysisUsage(AnalysisUsage &AU) const {
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AU.addRequired<DominatorTree>();
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AU.addRequired<DominanceFrontier>();
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AU.addRequired<TargetData>();
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AU.setPreservesCFG();
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@ -42,6 +43,9 @@ bool PromotePass::runOnFunction(Function &F) {
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bool Changed = false;
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DominatorTree &DT = getAnalysis<DominatorTree>();
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DominanceFrontier &DF = getAnalysis<DominanceFrontier>();
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while (1) {
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Allocas.clear();
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@ -54,7 +58,7 @@ bool PromotePass::runOnFunction(Function &F) {
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if (Allocas.empty()) break;
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PromoteMemToReg(Allocas, getAnalysis<DominanceFrontier>(), TD);
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PromoteMemToReg(Allocas, DT, DF, TD);
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NumPromoted += Allocas.size();
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Changed = true;
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}
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@ -361,7 +361,8 @@ void PromoteMem2Reg::RenamePass(BasicBlock *BB, BasicBlock *Pred,
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/// of the function at all. All allocas must be from the same function.
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///
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void PromoteMemToReg(const std::vector<AllocaInst*> &Allocas,
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DominanceFrontier &DF, const TargetData &TD) {
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DominatorTree &DT, DominanceFrontier &DF,
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const TargetData &TD) {
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// If there is nothing to do, bail out...
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if (Allocas.empty()) return;
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PromoteMem2Reg(Allocas, DF, TD).run();
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