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Fix ARM's b.w instruction for thumb 2 and the encoding T4. The branch target

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is 24 bits not 20 and the decoding needed to correctly handle converting the
J1 and J2 bits to their I1 and I2 values to reconstruct the displacement. 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166982 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Kevin Enderby 2012-10-29 23:27:20 +00:00
parent c1ed096b6b
commit 445ba85b8d
4 changed files with 38 additions and 11 deletions
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4
lib/Target/ARM/ARMInstrThumb2.td
View File

@ -3245,11 +3245,11 @@ def t2B : T2I<(outs), (ins uncondbrtarget:$target), IIC_Br,
let Inst{15-14} = 0b10;
let Inst{12} = 1;
bits<20> target;
bits<24> target;
let Inst{26} = target{19};
let Inst{11} = target{18};
let Inst{13} = target{17};
let Inst{21-16} = target{16-11};
let Inst{25-16} = target{20-11};
let Inst{10-0} = target{10-0};
let DecoderMethod = "DecodeT2BInstruction";
}

30
lib/Target/ARM/Disassembler/ARMDisassembler.cpp
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@ -2095,16 +2095,28 @@ static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val,
static DecodeStatus
DecodeT2BInstruction(MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder) {
DecodeStatus S = MCDisassembler::Success;
unsigned imm = (fieldFromInstruction(Insn, 0, 11) << 0) |
(fieldFromInstruction(Insn, 11, 1) << 18) |
(fieldFromInstruction(Insn, 13, 1) << 17) |
(fieldFromInstruction(Insn, 16, 6) << 11) |
(fieldFromInstruction(Insn, 26, 1) << 19);
if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<20>(imm<<1) + 4,
DecodeStatus Status = MCDisassembler::Success;
// Note the J1 and J2 values are from the encoded instruction. So here
// change them to I1 and I2 values via as documented:
// I1 = NOT(J1 EOR S);
// I2 = NOT(J2 EOR S);
// and build the imm32 with one trailing zero as documented:
// imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32);
unsigned S = fieldFromInstruction(Insn, 26, 1);
unsigned J1 = fieldFromInstruction(Insn, 13, 1);
unsigned J2 = fieldFromInstruction(Insn, 11, 1);
unsigned I1 = !(J1 ^ S);
unsigned I2 = !(J2 ^ S);
unsigned imm10 = fieldFromInstruction(Insn, 16, 10);
unsigned imm11 = fieldFromInstruction(Insn, 0, 11);
unsigned tmp = (S << 23) | (I1 << 22) | (I2 << 21) | (imm10 << 11) | imm11;
int imm32 = SignExtend32<24>(tmp << 1);
if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4,
true, 4, Inst, Decoder))
Inst.addOperand(MCOperand::CreateImm(SignExtend32<20>(imm << 1)));
return S;
Inst.addOperand(MCOperand::CreateImm(imm32));
return Status;
}
static DecodeStatus

12
test/MC/ARM/thumb2-b.w-encodingT4.s Normal file
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@ -0,0 +1,12 @@
@ RUN: llvm-mc -triple=thumbv7-apple-darwin -mcpu=cortex-a8 -show-encoding < %s | FileCheck %s
.syntax unified
.globl _func
.thumb_func _foo
.space 0x37c6
_foo:
@------------------------------------------------------------------------------
@ B (thumb2 b.w encoding T4) rdar://12585795
@------------------------------------------------------------------------------
b.w 0x3680c
@ CHECK: b.w #223244 @ encoding: [0x6d,0xf0,0x0c,0xb0]

3
test/MC/Disassembler/ARM/thumb2.txt
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@ -169,6 +169,9 @@
0x13 0xf5 0xce 0xa9
# CHECK: b.w #208962
0x33 0xf0 0x21 0xb8 # rdar://12585795
#------------------------------------------------------------------------------
# BFC