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Add support for floating point base register + offset register addressing mode
load and store instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151611 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -30,6 +30,7 @@
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/SelectionDAGISel.h"
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#include "llvm/CodeGen/SelectionDAGNodes.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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@ -91,7 +92,7 @@ private:
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SDNode *Select(SDNode *N);
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// Complex Pattern.
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bool SelectAddr(SDValue N, SDValue &Base, SDValue &Offset);
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bool SelectAddr(SDNode *Parent, SDValue N, SDValue &Base, SDValue &Offset);
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// getImm - Return a target constant with the specified value.
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inline SDValue getImm(const SDNode *Node, unsigned Imm) {
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@ -197,7 +198,7 @@ SDNode *MipsDAGToDAGISel::getGlobalBaseReg() {
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/// ComplexPattern used on MipsInstrInfo
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/// Used on Mips Load/Store instructions
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bool MipsDAGToDAGISel::
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SelectAddr(SDValue Addr, SDValue &Base, SDValue &Offset) {
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SelectAddr(SDNode *Parent, SDValue Addr, SDValue &Base, SDValue &Offset) {
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EVT ValTy = Addr.getValueType();
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// if Address is FI, get the TargetFrameIndex.
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@ -256,6 +257,12 @@ SelectAddr(SDValue Addr, SDValue &Base, SDValue &Offset) {
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return true;
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}
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}
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// If an indexed load/store can be emitted, return false.
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if (const LSBaseSDNode* LS = dyn_cast<LSBaseSDNode>(Parent))
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if ((LS->getMemoryVT() == MVT::f32 || LS->getMemoryVT() == MVT::f64) &&
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Subtarget.hasMips32r2Or64())
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return false;
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}
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Base = Addr;
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@ -261,7 +261,18 @@ MipsTargetLowering(MipsTargetMachine &TM)
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bool MipsTargetLowering::allowsUnalignedMemoryAccesses(EVT VT) const {
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MVT::SimpleValueType SVT = VT.getSimpleVT().SimpleTy;
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return SVT == MVT::i64 || SVT == MVT::i32 || SVT == MVT::i16;
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switch (SVT) {
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case MVT::i64:
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case MVT::i32:
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case MVT::i16:
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return true;
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case MVT::f32:
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case MVT::f64:
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return Subtarget->hasMips32r2Or64();
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default:
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return false;
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}
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}
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EVT MipsTargetLowering::getSetCCResultType(EVT VT) const {
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@ -94,6 +94,24 @@ class FPStore<bits<6> op, string opstr, RegisterClass RC, Operand MemOpnd>:
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!strconcat(opstr, "\t$ft, $addr"), [(store RC:$ft, addr:$addr)],
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IIStore>;
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// FP indexed load.
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class FPIdxLoad<bits<6> funct, string opstr, RegisterClass DRC,
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RegisterClass PRC, PatFrag FOp>:
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FFMemIdx<funct, (outs DRC:$fd), (ins PRC:$base, PRC:$index),
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!strconcat(opstr, "\t$fd, $index($base)"),
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[(set DRC:$fd, (FOp (add PRC:$base, PRC:$index)))]> {
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let fs = 0;
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}
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// FP indexed store.
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class FPIdxStore<bits<6> funct, string opstr, RegisterClass DRC,
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RegisterClass PRC, PatFrag FOp>:
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FFMemIdx<funct, (outs), (ins DRC:$fs, PRC:$base, PRC:$index),
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!strconcat(opstr, "\t$fs, $index($base)"),
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[(FOp DRC:$fs, (add PRC:$base, PRC:$index))]> {
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let fd = 0;
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}
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// Instructions that convert an FP value to 32-bit fixed point.
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multiclass FFR1_W_M<bits<6> funct, string opstr> {
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def _S : FFR1<funct, 16, opstr, "w.s", FGR32, FGR32>;
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@ -240,6 +258,34 @@ let Predicates = [NotN64, NotMips64] in {
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def SDC1 : FPStore<0x3d, "sdc1", AFGR64, mem>;
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}
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// Indexed loads and stores.
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let Predicates = [HasMips32r2Or64] in {
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def LWXC1 : FPIdxLoad<0x0, "lwxc1", FGR32, CPURegs, load_a>;
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def LUXC1 : FPIdxLoad<0x5, "luxc1", FGR32, CPURegs, load_u>;
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def SWXC1 : FPIdxStore<0x8, "swxc1", FGR32, CPURegs, store_a>;
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def SUXC1 : FPIdxStore<0xd, "suxc1", FGR32, CPURegs, store_u>;
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}
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let Predicates = [HasMips32r2, NotMips64] in {
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def LDXC1 : FPIdxLoad<0x1, "ldxc1", AFGR64, CPURegs, load_a>;
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def SDXC1 : FPIdxStore<0x9, "sdxc1", AFGR64, CPURegs, store_a>;
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}
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let Predicates = [HasMips64, NotN64] in {
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def LDXC164 : FPIdxLoad<0x1, "ldxc1", FGR64, CPURegs, load_a>;
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def SDXC164 : FPIdxStore<0x9, "sdxc1", FGR64, CPURegs, store_a>;
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}
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// n64
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let Predicates = [IsN64] in {
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def LWXC1_P8 : FPIdxLoad<0x0, "lwxc1", FGR32, CPU64Regs, load_a>;
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def LUXC1_P8 : FPIdxLoad<0x5, "luxc1", FGR32, CPU64Regs, load_u>;
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def LDXC164_P8 : FPIdxLoad<0x1, "ldxc1", FGR64, CPU64Regs, load_a>;
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def SWXC1_P8 : FPIdxStore<0x8, "swxc1", FGR32, CPU64Regs, store_a>;
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def SUXC1_P8 : FPIdxStore<0xd, "suxc1", FGR32, CPU64Regs, store_u>;
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def SDXC164_P8 : FPIdxStore<0x9, "sdxc1", FGR64, CPU64Regs, store_a>;
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}
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/// Floating-point Aritmetic
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defm FADD : FFR2P_M<0x00, "add", fadd, 1>;
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defm FDIV : FFR2P_M<0x03, "div", fdiv>;
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@ -308,3 +308,23 @@ class FFMADDSUB<bits<3> funct, bits<3> fmt, dag outs, dag ins, string asmstr,
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let Inst{5-3} = funct;
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let Inst{2-0} = fmt;
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}
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// FP indexed load/store instructions.
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class FFMemIdx<bits<6> _funct, dag outs, dag ins, string asmstr,
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list<dag> pattern> :
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MipsInst<outs, ins, asmstr, pattern, NoItinerary, FrmOther>
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{
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bits<5> base;
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bits<5> index;
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bits<5> fs;
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bits<5> fd;
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bits<6> funct;
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let Opcode = 0x13;
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let Inst{25-21} = base;
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let Inst{20-16} = index;
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let Inst{15-11} = fs;
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let Inst{10-6} = fd;
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let Inst{5-0} = funct;
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}
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@ -128,6 +128,7 @@ def HasCondMov : Predicate<"Subtarget.hasCondMov()">;
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def HasMips32 : Predicate<"Subtarget.hasMips32()">;
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def HasMips32r2 : Predicate<"Subtarget.hasMips32r2()">;
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def HasMips64 : Predicate<"Subtarget.hasMips64()">;
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def HasMips32r2Or64 : Predicate<"Subtarget.hasMips32r2Or64()">;
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def NotMips64 : Predicate<"!Subtarget.hasMips64()">;
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def HasMips64r2 : Predicate<"Subtarget.hasMips64r2()">;
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def IsN64 : Predicate<"Subtarget.isABI_N64()">;
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@ -231,7 +232,7 @@ def immZExt5 : ImmLeaf<i32, [{return Imm == (Imm & 0x1f);}]>;
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// Mips Address Mode! SDNode frameindex could possibily be a match
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// since load and store instructions from stack used it.
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def addr : ComplexPattern<iPTR, 2, "SelectAddr", [frameindex], []>;
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def addr : ComplexPattern<iPTR, 2, "SelectAddr", [frameindex], [SDNPWantParent]>;
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//===----------------------------------------------------------------------===//
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// Pattern fragment for load/store
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@ -112,6 +112,8 @@ public:
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bool hasMips64() const { return MipsArchVersion >= Mips64; }
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bool hasMips64r2() const { return MipsArchVersion == Mips64r2; }
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bool hasMips32r2Or64() const { return hasMips32r2() || hasMips64(); }
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bool isLittle() const { return IsLittle; }
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bool isFP64bit() const { return IsFP64bit; }
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bool isGP64bit() const { return IsGP64bit; }
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59
test/CodeGen/Mips/fp-indexed-ls.ll
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59
test/CodeGen/Mips/fp-indexed-ls.ll
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@ -0,0 +1,59 @@
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; RUN: llc -march=mipsel -mcpu=mips32r2 < %s | FileCheck %s
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%struct.S = type <{ [4 x float] }>
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@s = external global [4 x %struct.S]
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@gf = external global float
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@gd = external global double
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define float @foo0(float* nocapture %b, i32 %o) nounwind readonly {
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entry:
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; CHECK: lwxc1
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%arrayidx = getelementptr inbounds float* %b, i32 %o
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%0 = load float* %arrayidx, align 4
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ret float %0
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}
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define double @foo1(double* nocapture %b, i32 %o) nounwind readonly {
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entry:
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; CHECK: ldxc1
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%arrayidx = getelementptr inbounds double* %b, i32 %o
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%0 = load double* %arrayidx, align 8
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ret double %0
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}
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define float @foo2(i32 %b, i32 %c) nounwind readonly {
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entry:
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; CHECK: luxc1
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%arrayidx1 = getelementptr inbounds [4 x %struct.S]* @s, i32 0, i32 %b, i32 0, i32 %c
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%0 = load float* %arrayidx1, align 1
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ret float %0
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}
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define void @foo3(float* nocapture %b, i32 %o) nounwind {
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entry:
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; CHECK: swxc1
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%0 = load float* @gf, align 4
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%arrayidx = getelementptr inbounds float* %b, i32 %o
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store float %0, float* %arrayidx, align 4
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ret void
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}
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define void @foo4(double* nocapture %b, i32 %o) nounwind {
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entry:
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; CHECK: sdxc1
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%0 = load double* @gd, align 8
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%arrayidx = getelementptr inbounds double* %b, i32 %o
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store double %0, double* %arrayidx, align 8
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ret void
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}
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define void @foo5(i32 %b, i32 %c) nounwind {
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entry:
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; CHECK: suxc1
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%0 = load float* @gf, align 4
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%arrayidx1 = getelementptr inbounds [4 x %struct.S]* @s, i32 0, i32 %b, i32 0, i32 %c
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store float %0, float* %arrayidx1, align 1
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ret void
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}
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67
test/CodeGen/Mips/mips64-fp-indexed-ls.ll
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67
test/CodeGen/Mips/mips64-fp-indexed-ls.ll
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@ -0,0 +1,67 @@
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; RUN: llc -march=mips64el -mcpu=mips64r2 -mattr=n64 < %s | FileCheck %s
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%struct.S = type <{ [4 x float] }>
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@s = external global [4 x %struct.S]
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@gf = external global float
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@gd = external global double
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define float @foo0(float* nocapture %b, i32 %o) nounwind readonly {
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entry:
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; CHECK: lwxc1
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%idxprom = zext i32 %o to i64
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%arrayidx = getelementptr inbounds float* %b, i64 %idxprom
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%0 = load float* %arrayidx, align 4
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ret float %0
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}
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define double @foo1(double* nocapture %b, i32 %o) nounwind readonly {
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entry:
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; CHECK: ldxc1
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%idxprom = zext i32 %o to i64
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%arrayidx = getelementptr inbounds double* %b, i64 %idxprom
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%0 = load double* %arrayidx, align 8
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ret double %0
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}
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define float @foo2(i32 %b, i32 %c) nounwind readonly {
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entry:
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; CHECK: luxc1
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%idxprom = zext i32 %c to i64
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%idxprom1 = zext i32 %b to i64
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%arrayidx2 = getelementptr inbounds [4 x %struct.S]* @s, i64 0, i64 %idxprom1, i32 0, i64 %idxprom
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%0 = load float* %arrayidx2, align 1
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ret float %0
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}
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define void @foo3(float* nocapture %b, i32 %o) nounwind {
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entry:
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; CHECK: swxc1
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%0 = load float* @gf, align 4
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%idxprom = zext i32 %o to i64
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%arrayidx = getelementptr inbounds float* %b, i64 %idxprom
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store float %0, float* %arrayidx, align 4
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ret void
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}
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define void @foo4(double* nocapture %b, i32 %o) nounwind {
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entry:
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; CHECK: sdxc1
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%0 = load double* @gd, align 8
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%idxprom = zext i32 %o to i64
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%arrayidx = getelementptr inbounds double* %b, i64 %idxprom
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store double %0, double* %arrayidx, align 8
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ret void
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}
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define void @foo5(i32 %b, i32 %c) nounwind {
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entry:
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; CHECK: suxc1
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%0 = load float* @gf, align 4
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%idxprom = zext i32 %c to i64
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%idxprom1 = zext i32 %b to i64
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%arrayidx2 = getelementptr inbounds [4 x %struct.S]* @s, i64 0, i64 %idxprom1, i32 0, i64 %idxprom
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store float %0, float* %arrayidx2, align 1
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ret void
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}
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