6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-07-22 09:29:31 +00:00
Code Issues Projects Releases Wiki Activity

[AArch64] Fix the ordering of the accumulate operand in SchedRW list.

Browse Source 
Patch by Dave Estes <cestes@codeaurora.org>
http://reviews.llvm.org/D4037

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210446 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chad Rosier 2014-06-09 01:54:00 +00:00
parent 0607e82c0a
commit 451cc566c1
2 changed files with 7 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
lib/Target/AArch64/AArch64InstrFormats.td
View File

@ -1323,13 +1323,13 @@ class BaseMulAccum<bit isSub, bits<3> opc, RegisterClass multype,
multiclass MulAccum<bit isSub, string asm, SDNode AccNode> {
def Wrrr : BaseMulAccum<isSub, 0b000, GPR32, GPR32, asm,
[(set GPR32:$Rd, (AccNode GPR32:$Ra, (mul GPR32:$Rn, GPR32:$Rm)))]>,
Sched<[WriteIM32, ReadIMA, ReadIM, ReadIM]> {
Sched<[WriteIM32, ReadIM, ReadIM, ReadIMA]> {
let Inst{31} = 0;
}
def Xrrr : BaseMulAccum<isSub, 0b000, GPR64, GPR64, asm,
[(set GPR64:$Rd, (AccNode GPR64:$Ra, (mul GPR64:$Rn, GPR64:$Rm)))]>,
Sched<[WriteIM64, ReadIMA, ReadIM, ReadIM]> {
Sched<[WriteIM64, ReadIM, ReadIM, ReadIMA]> {
let Inst{31} = 1;
}
}
@ -1339,7 +1339,7 @@ class WideMulAccum<bit isSub, bits<3> opc, string asm,
: BaseMulAccum<isSub, opc, GPR32, GPR64, asm,
[(set GPR64:$Rd, (AccNode GPR64:$Ra,
(mul (ExtNode GPR32:$Rn), (ExtNode GPR32:$Rm))))]>,
Sched<[WriteIM32, ReadIMA, ReadIM, ReadIM]> {
Sched<[WriteIM32, ReadIM, ReadIM, ReadIMA]> {
let Inst{31} = 1;
}

7
test/CodeGen/AArch64/arm64-misched-forwarding-A53.ll
View File

@ -6,9 +6,10 @@
;
; CHECK: ********** MI Scheduling **********
; CHECK: shiftable
; CHECK: *** Final schedule for BB#0 ***
; CHECK: ADDXrr %vreg0, %vreg2
; CHECK: ADDXrs %vreg0, %vreg2, 5
; CHECK: SU(2): %vreg2<def> = SUBXri %vreg1, 20, 0
; CHECK: Successors:
; CHECK-NEXT: val SU(4): Latency=1 Reg=%vreg2
; CHECK-NEXT: val SU(3): Latency=2 Reg=%vreg2
; CHECK: ********** INTERVALS **********
define i64 @shiftable(i64 %A, i64 %B) {
%tmp0 = sub i64 %B, 20