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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121167 91177308-0d34-0410-b5e6-96231b3b80d8
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76612b549f
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@ -66,23 +66,23 @@ struct OperandsSignature {
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return true;
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}
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}
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const CodeGenRegisterClass *DstRC = 0;
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for (unsigned i = 0, e = InstPatNode->getNumChildren(); i != e; ++i) {
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TreePatternNode *Op = InstPatNode->getChild(i);
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// For now, filter out any operand with a predicate.
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// For now, filter out any operand with multiple values.
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if (!Op->getPredicateFns().empty() ||
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Op->getNumTypes() != 1)
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return false;
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assert(Op->hasTypeSet(0) && "Type infererence not done?");
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// For now, all the operands must have the same type.
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if (Op->getType(0) != VT)
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return false;
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if (!Op->isLeaf()) {
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if (Op->getOperator()->getName() == "imm") {
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Operands.push_back("i");
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@ -108,7 +108,7 @@ struct OperandsSignature {
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RC = Target.getRegisterClassForRegister(OpLeafRec);
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else
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return false;
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// For now, this needs to be a register class of some sort.
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if (!RC)
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return false;
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@ -213,7 +213,7 @@ class FastISelMap {
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typedef std::map<MVT::SimpleValueType, PredMap> RetPredMap;
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typedef std::map<MVT::SimpleValueType, RetPredMap> TypeRetPredMap;
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typedef std::map<std::string, TypeRetPredMap> OpcodeTypeRetPredMap;
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typedef std::map<OperandsSignature, OpcodeTypeRetPredMap>
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typedef std::map<OperandsSignature, OpcodeTypeRetPredMap>
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OperandsOpcodeTypeRetPredMap;
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OperandsOpcodeTypeRetPredMap SimplePatterns;
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@ -266,7 +266,7 @@ void FastISelMap::CollectPatterns(CodeGenDAGPatterns &CGP) {
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CodeGenInstruction &II = CGP.getTargetInfo().getInstruction(Op);
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if (II.Operands.size() == 0)
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continue;
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// For now, ignore multi-instruction patterns.
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bool MultiInsts = false;
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for (unsigned i = 0, e = Dst->getNumChildren(); i != e; ++i) {
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@ -296,7 +296,7 @@ void FastISelMap::CollectPatterns(CodeGenDAGPatterns &CGP) {
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// If this isn't a leaf, then continue since the register classes are
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// a bit too complicated for now.
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if (!Dst->getChild(1)->isLeaf()) continue;
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DefInit *SR = dynamic_cast<DefInit*>(Dst->getChild(1)->getLeafValue());
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if (SR)
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SubRegNo = getQualifiedName(SR->getDef());
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@ -311,7 +311,7 @@ void FastISelMap::CollectPatterns(CodeGenDAGPatterns &CGP) {
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// Ignore multiple result nodes for now.
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if (InstPatNode->getNumTypes() > 1) continue;
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Record *InstPatOp = InstPatNode->getOperator();
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std::string OpcodeName = getOpcodeName(InstPatOp, CGP);
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MVT::SimpleValueType RetVT = MVT::isVoid;
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@ -335,7 +335,7 @@ void FastISelMap::CollectPatterns(CodeGenDAGPatterns &CGP) {
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OperandsSignature Operands;
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if (!Operands.initialize(InstPatNode, Target, VT))
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continue;
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std::vector<std::string>* PhysRegInputs = new std::vector<std::string>();
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if (!InstPatNode->isLeaf() &&
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(InstPatNode->getOperator()->getName() == "imm" ||
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@ -348,7 +348,7 @@ void FastISelMap::CollectPatterns(CodeGenDAGPatterns &CGP) {
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PhysRegInputs->push_back("");
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continue;
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}
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DefInit *OpDI = dynamic_cast<DefInit*>(Op->getLeafValue());
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Record *OpLeafRec = OpDI->getDef();
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std::string PhysReg;
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@ -356,7 +356,7 @@ void FastISelMap::CollectPatterns(CodeGenDAGPatterns &CGP) {
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PhysReg += static_cast<StringInit*>(OpLeafRec->getValue( \
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"Namespace")->getValue())->getValue();
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PhysReg += "::";
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std::vector<CodeGenRegister> Regs = Target.getRegisters();
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for (unsigned i = 0; i < Regs.size(); ++i) {
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if (Regs[i].TheDef == OpLeafRec) {
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@ -365,7 +365,7 @@ void FastISelMap::CollectPatterns(CodeGenDAGPatterns &CGP) {
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}
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}
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}
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PhysRegInputs->push_back(PhysReg);
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}
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} else
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@ -435,7 +435,7 @@ void FastISelMap::PrintFunctionDefinitions(raw_ostream &OS) {
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PI != PE; ++PI) {
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std::string PredicateCheck = PI->first;
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const InstructionMemo &Memo = PI->second;
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if (PredicateCheck.empty()) {
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assert(!HasPred &&
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"Multiple instructions match, at least one has "
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@ -445,14 +445,14 @@ void FastISelMap::PrintFunctionDefinitions(raw_ostream &OS) {
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OS << " ";
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HasPred = true;
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}
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for (unsigned i = 0; i < Memo.PhysRegs->size(); ++i) {
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if ((*Memo.PhysRegs)[i] != "")
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OS << " BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, "
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<< "TII.get(TargetOpcode::COPY), "
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<< (*Memo.PhysRegs)[i] << ").addReg(Op" << i << ");\n";
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}
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OS << " return FastEmitInst_";
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if (Memo.SubRegNo.empty()) {
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Operands.PrintManglingSuffix(OS, *Memo.PhysRegs);
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@ -468,10 +468,10 @@ void FastISelMap::PrintFunctionDefinitions(raw_ostream &OS) {
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OS << Memo.SubRegNo;
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OS << ");\n";
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}
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if (HasPred)
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OS << " }\n";
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}
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// Return 0 if none of the predicates were satisfied.
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if (HasPred)
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@ -479,7 +479,7 @@ void FastISelMap::PrintFunctionDefinitions(raw_ostream &OS) {
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OS << "}\n";
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OS << "\n";
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}
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// Emit one function for the type that demultiplexes on return type.
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OS << "unsigned FastEmit_"
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<< getLegalCName(Opcode) << "_"
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@ -502,7 +502,7 @@ void FastISelMap::PrintFunctionDefinitions(raw_ostream &OS) {
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OS << ");\n";
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}
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OS << " default: return 0;\n}\n}\n\n";
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} else {
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// Non-variadic return type.
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OS << "unsigned FastEmit_"
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@ -514,13 +514,13 @@ void FastISelMap::PrintFunctionDefinitions(raw_ostream &OS) {
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OS << ", ";
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Operands.PrintParameters(OS);
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OS << ") {\n";
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OS << " if (RetVT.SimpleTy != " << getName(RM.begin()->first)
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<< ")\n return 0;\n";
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const PredMap &PM = RM.begin()->second;
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bool HasPred = false;
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// Emit code for each possible instruction. There may be
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// multiple if there are subtarget concerns.
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for (PredMap::const_iterator PI = PM.begin(), PE = PM.end(); PI != PE;
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@ -537,16 +537,16 @@ void FastISelMap::PrintFunctionDefinitions(raw_ostream &OS) {
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OS << " ";
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HasPred = true;
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}
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for (unsigned i = 0; i < Memo.PhysRegs->size(); ++i) {
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if ((*Memo.PhysRegs)[i] != "")
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OS << " BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, "
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<< "TII.get(TargetOpcode::COPY), "
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<< (*Memo.PhysRegs)[i] << ").addReg(Op" << i << ");\n";
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}
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OS << " return FastEmitInst_";
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if (Memo.SubRegNo.empty()) {
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Operands.PrintManglingSuffix(OS, *Memo.PhysRegs);
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OS << "(" << InstNS << Memo.Name << ", ";
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@ -560,11 +560,11 @@ void FastISelMap::PrintFunctionDefinitions(raw_ostream &OS) {
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OS << Memo.SubRegNo;
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OS << ");\n";
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}
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if (HasPred)
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OS << " }\n";
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}
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// Return 0 if none of the predicates were satisfied.
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if (HasPred)
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OS << " return 0;\n";
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