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reverting 172579
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172594 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1071,9 +1071,6 @@ MipsAsmParser::parseHWRegs(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
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MipsAsmParser::OperandMatchResultTy
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MipsAsmParser::parseHW64Regs(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
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if (!isMips64())
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return MatchOperand_NoMatch;
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//if the first token is not '$' we have error
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if (Parser.getTok().isNot(AsmToken::Dollar))
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return MatchOperand_NoMatch;
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@ -1091,7 +1088,7 @@ MipsAsmParser::parseHW64Regs(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
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MipsOperand *op = MipsOperand::CreateReg(Mips::HWR29_64, S,
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Parser.getTok().getLoc());
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op->setRegKind(MipsOperand::Kind_HW64Regs);
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op->setRegKind(MipsOperand::Kind_HWRegs);
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Operands.push_back(op);
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Parser.Lex(); // Eat reg number
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@ -128,11 +128,6 @@ static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeHWRegs64RegisterClass(MCInst &Inst,
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unsigned Insn,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeACRegsRegisterClass(MCInst &Inst,
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unsigned RegNo,
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uint64_t Address,
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@ -459,17 +454,6 @@ static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst,
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeHWRegs64RegisterClass(MCInst &Inst,
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unsigned RegNo,
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uint64_t Address,
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const void *Decoder) {
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//Currently only hardware register 29 is supported
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if (RegNo != 29)
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return MCDisassembler::Fail;
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Inst.addOperand(MCOperand::CreateReg(Mips::HWR29_64));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeACRegsRegisterClass(MCInst &Inst,
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unsigned RegNo,
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uint64_t Address,
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@ -373,6 +373,6 @@ def HWRegsOpnd : RegisterOperand<HWRegs, "printCPURegs"> {
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let ParserMatchClass = HWRegsAsmOperand;
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}
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def HW64RegsOpnd : RegisterOperand<HWRegs64, "printCPURegs"> {
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def HW64RegsOpnd : RegisterOperand<HWRegs, "printCPURegs"> {
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let ParserMatchClass = HW64RegsAsmOperand;
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}
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@ -404,9 +404,3 @@
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# CHECK: xori $9, $6, 17767
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0x38 0xc9 0x45 0x67
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# CHECK: .set push
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# CHECK: .set mips32r2
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# CHECK: rdhwr $5, $29
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# CHECK: .set pop
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0x7c 0x05 0xe8 0x3b
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@ -404,9 +404,3 @@
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# CHECK: xori $9, $6, 17767
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0x67 0x45 0xc9 0x38
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# CHECK: .set push
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# CHECK: .set mips32r2
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# CHECK: rdhwr $5, $29
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# CHECK: .set pop
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0x3b 0xe8 0x05 0x7c
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@ -81,10 +81,6 @@
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# CHECK: sub $6, $zero, $7 # encoding: [0x22,0x30,0x07,0x00]
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# CHECK: subu $6, $zero, $7 # encoding: [0x23,0x30,0x07,0x00]
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# CHECK: addu $7, $8, $zero # encoding: [0x21,0x38,0x00,0x01]
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# CHECK: .set push
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# CHECK: .set mips32r2
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# CHECK: rdhwr $5, $29
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# CHECK: .set pop # encoding: [0x3b,0xe8,0x05,0x7c]
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add $9,$6,$7
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add $9,$6,17767
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addu $9,$6,-15001
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@ -102,4 +98,3 @@
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neg $6,$7
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negu $6,$7
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move $7,$8
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rdhwr $5, $29
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@ -78,11 +78,6 @@
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# CHECK: multu $3, $5 # encoding: [0x19,0x00,0x65,0x00]
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# CHECK: dsubu $4, $3, $5 # encoding: [0x2f,0x20,0x65,0x00]
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# CHECK: daddu $7, $8, $zero # encoding: [0x2d,0x38,0x00,0x01]
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# CHECK: .set push
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# CHECK: .set mips32r2
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# CHECK: rdhwr $5, $29
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# CHECK: .set pop # encoding: [0x3b,0xe8,0x05,0x7c]
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dadd $9,$6,$7
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dadd $9,$6,17767
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daddu $9,$6,-15001
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@ -97,4 +92,3 @@
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multu $3,$5
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dsubu $4,$3,$5
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move $7,$8
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rdhwr $5, $29
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