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Remove special handling of implicit_def. Fix a couple more bugs in liveintervalanalysis and coalescer handling of implicit_def.

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Note, isUndef marker must be placed even on implicit_def def operand or else the scavenger will not ignore it. This is necessary because -O0 path does not use liveintervalanalysis, it treats implicit_def just like any other def.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74601 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng
2009-07-01 08:19:36 +00:00
parent d6bb283de9
commit 459a7c6b6a
5 changed files with 175 additions and 64 deletions
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31
lib/CodeGen/RegisterScavenging.cpp
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@@ -57,28 +57,22 @@ static bool RedefinesSuperRegPart(const MachineInstr *MI,
}
/// setUsed - Set the register and its sub-registers as being used.
void RegScavenger::setUsed(unsigned Reg, bool ImpDef) {
void RegScavenger::setUsed(unsigned Reg) {
RegsAvailable.reset(Reg);
ImplicitDefed[Reg] = ImpDef;
for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
unsigned SubReg = *SubRegs; ++SubRegs) {
unsigned SubReg = *SubRegs; ++SubRegs)
RegsAvailable.reset(SubReg);
ImplicitDefed[SubReg] = ImpDef;
}
}
/// setUnused - Set the register and its sub-registers as being unused.
void RegScavenger::setUnused(unsigned Reg, const MachineInstr *MI) {
RegsAvailable.set(Reg);
ImplicitDefed.reset(Reg);
for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
unsigned SubReg = *SubRegs; ++SubRegs)
if (!RedefinesSuperRegPart(MI, Reg, TRI)) {
if (!RedefinesSuperRegPart(MI, Reg, TRI))
RegsAvailable.set(SubReg);
ImplicitDefed.reset(SubReg);
}
}
void RegScavenger::enterBasicBlock(MachineBasicBlock *mbb) {
@@ -94,7 +88,6 @@ void RegScavenger::enterBasicBlock(MachineBasicBlock *mbb) {
if (!MBB) {
NumPhysRegs = TRI->getNumRegs();
RegsAvailable.resize(NumPhysRegs);
ImplicitDefed.resize(NumPhysRegs);
// Create reserved registers bitvector.
ReservedRegs = TRI->getReservedRegs(MF);
@@ -113,7 +106,6 @@ void RegScavenger::enterBasicBlock(MachineBasicBlock *mbb) {
ScavengeRestore = NULL;
CurrDist = 0;
DistanceMap.clear();
ImplicitDefed.reset();
// All registers started out unused.
RegsAvailable.set();
@@ -195,7 +187,10 @@ void RegScavenger::forward() {
ScavengeRestore = NULL;
}
bool IsImpDef = MI->getOpcode() == TargetInstrInfo::IMPLICIT_DEF;
#if 0
if (MI->getOpcode() == TargetInstrInfo::IMPLICIT_DEF)
return;
#endif
// Separate register operands into 3 classes: uses, defs, earlyclobbers.
SmallVector<std::pair<const MachineOperand*,unsigned>, 4> UseMOs;
@@ -221,14 +216,7 @@ void RegScavenger::forward() {
assert(isUsed(Reg) && "Using an undefined register!");
// Kill of implicit_def defined registers are ignored. e.g.
// entry: 0x2029ab8, LLVM BB @0x1b06080, ID#0:
// Live Ins: %R0
// %R0<def> = IMPLICIT_DEF
// %R0<def> = IMPLICIT_DEF
// STR %R0<kill>, %R0, %reg0, 0, 14, %reg0, Mem:ST(4,4) [0x1b06510 + 0]
// %R1<def> = LDR %R0, %reg0, 24, 14, %reg0, Mem:LD(4,4) [0x1b065bc + 0]
if (MO.isKill() && !isReserved(Reg) && !isImplicitlyDefined(Reg)) {
if (MO.isKill() && !isReserved(Reg)) {
KillRegs.set(Reg);
// Mark sub-registers as used.
@@ -278,10 +266,9 @@ void RegScavenger::forward() {
// Implicit def is allowed to "re-define" any register. Similarly,
// implicitly defined registers can be clobbered.
assert((isReserved(Reg) || isUnused(Reg) ||
IsImpDef || isImplicitlyDefined(Reg) ||
isLiveInButUnusedBefore(Reg, MI, MBB, TRI, MRI)) &&
"Re-defining a live register!");
setUsed(Reg, IsImpDef);
setUsed(Reg);
}
}