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Inline asm instructions may have additional <imp-def,kill> register operands. These operands are not marked with a flag like the normal asm operands, so we must not assert that there is a flag. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76373 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -732,7 +732,9 @@ isRegTiedToUseOperand(unsigned DefOpIdx, unsigned *UseOpIdx) const {
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unsigned DefPart = 0;
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for (unsigned i = 1, e = getNumOperands(); i < e; ) {
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const MachineOperand &FMO = getOperand(i);
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assert(FMO.isImm());
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// After the normal asm operands there may be additional imp-def regs.
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if (!FMO.isImm())
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return false;
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// Skip over this def.
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unsigned NumOps = InlineAsm::getNumOperandRegisters(FMO.getImm());
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unsigned PrevDef = i + 1;
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@ -788,7 +790,9 @@ isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx) const {
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unsigned FlagIdx, NumOps=0;
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for (FlagIdx = 1; FlagIdx < UseOpIdx; FlagIdx += NumOps+1) {
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const MachineOperand &UFMO = getOperand(FlagIdx);
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assert(UFMO.isImm() && "Expecting flag operand on inline asm");
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// After the normal asm operands there may be additional imp-def regs.
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if (!UFMO.isImm())
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return false;
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NumOps = InlineAsm::getNumOperandRegisters(UFMO.getImm());
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assert(NumOps < getNumOperands() && "Invalid inline asm flag");
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if (UseOpIdx < FlagIdx+NumOps+1)
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11
test/CodeGen/X86/2009-07-19-AsmExtraOperands.ll
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11
test/CodeGen/X86/2009-07-19-AsmExtraOperands.ll
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@ -0,0 +1,11 @@
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; RUN: llvm-as < %s | llc -march=x86-64
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; PR4583
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define i32 @atomic_cmpset_long(i64* %dst, i64 %exp, i64 %src) nounwind ssp noredzone noimplicitfloat {
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entry:
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%0 = call i8 asm sideeffect "\09lock ; \09\09\09cmpxchgq $2,$1 ;\09 sete\09$0 ;\09\091:\09\09\09\09# atomic_cmpset_long", "={ax},=*m,r,{ax},*m,~{memory},~{dirflag},~{fpsr},~{flags}"(i64* undef, i64 undef, i64 undef, i64* undef) nounwind ; <i8> [#uses=0]
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br label %1
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; <label>:1 ; preds = %entry
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ret i32 undef
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}
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