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add support for the "r" asm constraint
patch by Lauro Ramos Venancio git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32224 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -18,6 +18,7 @@
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#include "llvm/Function.h"
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#include "llvm/Constants.h"
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#include "llvm/Intrinsics.h"
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#include "llvm/ADT/VectorExtras.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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@ -37,6 +38,9 @@ namespace {
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ARMTargetLowering(TargetMachine &TM);
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virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
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virtual const char *getTargetNodeName(unsigned Opcode) const;
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std::vector<unsigned>
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getRegClassForInlineAsmConstraint(const std::string &Constraint,
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MVT::ValueType VT) const;
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};
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}
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@ -200,6 +204,29 @@ static ARMCC::CondCodes DAGIntCCToARMCC(ISD::CondCode CC) {
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}
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}
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std::vector<unsigned> ARMTargetLowering::
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getRegClassForInlineAsmConstraint(const std::string &Constraint,
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MVT::ValueType VT) const {
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if (Constraint.size() == 1) {
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// FIXME: handling only r regs
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switch (Constraint[0]) {
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default: break; // Unknown constraint letter
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case 'r': // GENERAL_REGS
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case 'R': // LEGACY_REGS
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if (VT == MVT::i32)
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return make_vector<unsigned>(ARM::R0, ARM::R1, ARM::R2, ARM::R3,
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ARM::R4, ARM::R5, ARM::R6, ARM::R7,
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ARM::R8, ARM::R9, ARM::R10, ARM::R11,
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ARM::R12, ARM::R13, ARM::R14, 0);
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break;
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}
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}
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return std::vector<unsigned>();
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}
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const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
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switch (Opcode) {
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default: return 0;
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7
test/CodeGen/ARM/arm-asm.ll
Normal file
7
test/CodeGen/ARM/arm-asm.ll
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@ -0,0 +1,7 @@
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; RUN: llvm-as < %s | llc -march=arm
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void %frame_dummy() {
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entry:
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%tmp1 = tail call void (sbyte*)* (void (sbyte*)*)* asm "", "=r,0,~{dirflag},~{fpsr},~{flags}"( void (sbyte*)* null )
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ret void
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}
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