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add support for the "r" asm constraint

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patch by Lauro Ramos Venancio


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32224 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Rafael Espindola 2006-12-05 17:37:31 +00:00
parent af21f4f6f9
commit 462af9a2e0
2 changed files with 34 additions and 0 deletions
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27
lib/Target/ARM/ARMISelDAGToDAG.cpp
View File

@ -18,6 +18,7 @@
#include "llvm/Function.h"
#include "llvm/Constants.h"
#include "llvm/Intrinsics.h"
#include "llvm/ADT/VectorExtras.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
@ -37,6 +38,9 @@ namespace {
ARMTargetLowering(TargetMachine &TM);
virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
virtual const char *getTargetNodeName(unsigned Opcode) const;
std::vector<unsigned>
getRegClassForInlineAsmConstraint(const std::string &Constraint,
MVT::ValueType VT) const;
};
}
@ -200,6 +204,29 @@ static ARMCC::CondCodes DAGIntCCToARMCC(ISD::CondCode CC) {
}
}
std::vector<unsigned> ARMTargetLowering::
getRegClassForInlineAsmConstraint(const std::string &Constraint,
MVT::ValueType VT) const {
if (Constraint.size() == 1) {
// FIXME: handling only r regs
switch (Constraint[0]) {
default: break; // Unknown constraint letter
case 'r': // GENERAL_REGS
case 'R': // LEGACY_REGS
if (VT == MVT::i32)
return make_vector<unsigned>(ARM::R0, ARM::R1, ARM::R2, ARM::R3,
ARM::R4, ARM::R5, ARM::R6, ARM::R7,
ARM::R8, ARM::R9, ARM::R10, ARM::R11,
ARM::R12, ARM::R13, ARM::R14, 0);
break;
}
}
return std::vector<unsigned>();
}
const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
switch (Opcode) {
default: return 0;

7
test/CodeGen/ARM/arm-asm.ll Normal file
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@ -0,0 +1,7 @@
; RUN: llvm-as < %s | llc -march=arm
void %frame_dummy() {
entry:
%tmp1 = tail call void (sbyte*)* (void (sbyte*)*)* asm "", "=r,0,~{dirflag},~{fpsr},~{flags}"( void (sbyte*)* null )
ret void
}