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Look for many more moves to fold (previously, we only

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*or g0, x      add g0, x          recognized * as a move)
 or  x, g0     add  x, g0
 or  0, x      add  0, x
 or  x, 0      add  x, 0


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@18793 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Brian Gaeke 2004-12-11 05:19:03 +00:00
parent 4f70b63ebc
commit 4658ba13a8
2 changed files with 48 additions and 4 deletions
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26
lib/Target/Sparc/SparcInstrInfo.cpp
View File

@ -21,16 +21,38 @@ SparcV8InstrInfo::SparcV8InstrInfo()
: TargetInstrInfo(SparcV8Insts, sizeof(SparcV8Insts)/sizeof(SparcV8Insts[0])){
}
static bool isZeroImmed (const MachineOperand &op) {
return (op.isImmediate() && op.getImmedValue() == 0);
}
/// Return true if the instruction is a register to register move and
/// leave the source and dest operands in the passed parameters.
///
bool SparcV8InstrInfo::isMoveInstr(const MachineInstr &MI,
unsigned &SrcReg, unsigned &DstReg) const {
if (MI.getOpcode() == V8::ORrr) {
if (MI.getOperand(1).getReg() == V8::G0) { // X = or G0, Y -> X = Y
// We look for 3 kinds of patterns here:
// or with G0 or 0
// add with G0 or 0
// fmovs or FpMOVD (pseudo double move).
if (MI.getOpcode() == V8::ORrr || MI.getOpcode() == V8::ADDrr) {
if (MI.getOperand(1).getReg() == V8::G0) {
DstReg = MI.getOperand(0).getReg();
SrcReg = MI.getOperand(2).getReg();
return true;
} else if (MI.getOperand (2).getReg() == V8::G0) {
DstReg = MI.getOperand(0).getReg();
SrcReg = MI.getOperand(1).getReg();
return true;
}
} else if (MI.getOpcode() == V8::ORri || MI.getOpcode() == V8::ADDri) {
if (isZeroImmed (MI.getOperand (1))) {
DstReg = MI.getOperand(0).getReg();
SrcReg = MI.getOperand(2).getReg();
return true;
} else if (isZeroImmed (MI.getOperand (2))) {
DstReg = MI.getOperand(0).getReg();
SrcReg = MI.getOperand(1).getReg();
return true;
}
} else if (MI.getOpcode() == V8::FMOVS || MI.getOpcode() == V8::FpMOVD) {
SrcReg = MI.getOperand(1).getReg();

26
lib/Target/SparcV8/SparcV8InstrInfo.cpp
View File

@ -21,16 +21,38 @@ SparcV8InstrInfo::SparcV8InstrInfo()
: TargetInstrInfo(SparcV8Insts, sizeof(SparcV8Insts)/sizeof(SparcV8Insts[0])){
}
static bool isZeroImmed (const MachineOperand &op) {
return (op.isImmediate() && op.getImmedValue() == 0);
}
/// Return true if the instruction is a register to register move and
/// leave the source and dest operands in the passed parameters.
///
bool SparcV8InstrInfo::isMoveInstr(const MachineInstr &MI,
unsigned &SrcReg, unsigned &DstReg) const {
if (MI.getOpcode() == V8::ORrr) {
if (MI.getOperand(1).getReg() == V8::G0) { // X = or G0, Y -> X = Y
// We look for 3 kinds of patterns here:
// or with G0 or 0
// add with G0 or 0
// fmovs or FpMOVD (pseudo double move).
if (MI.getOpcode() == V8::ORrr || MI.getOpcode() == V8::ADDrr) {
if (MI.getOperand(1).getReg() == V8::G0) {
DstReg = MI.getOperand(0).getReg();
SrcReg = MI.getOperand(2).getReg();
return true;
} else if (MI.getOperand (2).getReg() == V8::G0) {
DstReg = MI.getOperand(0).getReg();
SrcReg = MI.getOperand(1).getReg();
return true;
}
} else if (MI.getOpcode() == V8::ORri || MI.getOpcode() == V8::ADDri) {
if (isZeroImmed (MI.getOperand (1))) {
DstReg = MI.getOperand(0).getReg();
SrcReg = MI.getOperand(2).getReg();
return true;
} else if (isZeroImmed (MI.getOperand (2))) {
DstReg = MI.getOperand(0).getReg();
SrcReg = MI.getOperand(1).getReg();
return true;
}
} else if (MI.getOpcode() == V8::FMOVS || MI.getOpcode() == V8::FpMOVD) {
SrcReg = MI.getOperand(1).getReg();