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Move MRI into RegAllocBase. Clean up debug output a bit.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121599 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen 2010-12-10 23:49:00 +00:00
parent 092e2cd569
commit 4680dec5fb
3 changed files with 12 additions and 31 deletions
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5
lib/CodeGen/RegAllocBase.h
View File

@ -84,6 +84,7 @@ protected:
};
const TargetRegisterInfo *TRI;
MachineRegisterInfo *MRI;
VirtRegMap *VRM;
LiveIntervals *LIS;
LiveUnionArray PhysReg2LiveUnion;
@ -92,12 +93,12 @@ protected:
// query on a new live virtual register.
OwningArrayPtr<LiveIntervalUnion::Query> Queries;
RegAllocBase(): TRI(0), VRM(0), LIS(0) {}
RegAllocBase(): TRI(0), MRI(0), VRM(0), LIS(0) {}
virtual ~RegAllocBase() {}
// A RegAlloc pass should call this before allocatePhysRegs.
void init(const TargetRegisterInfo &tri, VirtRegMap &vrm, LiveIntervals &lis);
void init(VirtRegMap &vrm, LiveIntervals &lis);
// Get an initialized query to check interferences between lvr and preg. Note
// that Query::init must be called at least once for each physical register

23
lib/CodeGen/RegAllocBasic.cpp
View File

@ -74,9 +74,6 @@ class RABasic : public MachineFunctionPass, public RegAllocBase
{
// context
MachineFunction *MF;
const TargetMachine *TM;
MachineRegisterInfo *MRI;
BitVector ReservedRegs;
// analyses
@ -206,9 +203,9 @@ void RegAllocBase::LiveUnionArray::init(LiveIntervalUnion::Allocator &allocator,
new(Array + r) LiveIntervalUnion(r, allocator);
}
void RegAllocBase::init(const TargetRegisterInfo &tri, VirtRegMap &vrm,
LiveIntervals &lis) {
TRI = &tri;
void RegAllocBase::init(VirtRegMap &vrm, LiveIntervals &lis) {
TRI = &vrm.getTargetRegInfo();
MRI = &vrm.getRegInfo();
VRM = &vrm;
LIS = &lis;
PhysReg2LiveUnion.init(UnionAllocator, TRI->getNumRegs());
@ -262,13 +259,15 @@ void RegAllocBase::allocatePhysRegs() {
// selectOrSplit requests the allocator to return an available physical
// register if possible and populate a list of new live intervals that
// result from splitting.
DEBUG(dbgs() << "\nselectOrSplit " << MRI->getRegClass(VirtReg.reg)->getName()
<< ':' << VirtReg << '\n');
typedef SmallVector<LiveInterval*, 4> VirtRegVec;
VirtRegVec SplitVRegs;
unsigned AvailablePhysReg = selectOrSplit(VirtReg, SplitVRegs);
if (AvailablePhysReg) {
DEBUG(dbgs() << "allocating: " << TRI->getName(AvailablePhysReg) <<
" " << VirtReg << '\n');
DEBUG(dbgs() << "allocating: " << TRI->getName(AvailablePhysReg)
<< " for " << VirtReg << '\n');
assert(!VRM->hasPhys(VirtReg.reg) && "duplicate vreg in union");
VRM->assignVirt2Phys(VirtReg.reg, AvailablePhysReg);
PhysReg2LiveUnion[AvailablePhysReg].unify(VirtReg);
@ -416,7 +415,6 @@ unsigned RABasic::selectOrSplit(LiveInterval &VirtReg,
// Check for an available register in this class.
const TargetRegisterClass *TRC = MRI->getRegClass(VirtReg.reg);
DEBUG(dbgs() << "RegClass: " << TRC->getName() << ' ');
for (TargetRegisterClass::iterator I = TRC->allocation_order_begin(*MF),
E = TRC->allocation_order_end(*MF);
@ -469,14 +467,9 @@ bool RABasic::runOnMachineFunction(MachineFunction &mf) {
<< ((Value*)mf.getFunction())->getName() << '\n');
MF = &mf;
TM = &mf.getTarget();
MRI = &mf.getRegInfo();
DEBUG(RMF = &getAnalysis<RenderMachineFunction>());
const TargetRegisterInfo *TRI = TM->getRegisterInfo();
RegAllocBase::init(*TRI, getAnalysis<VirtRegMap>(),
getAnalysis<LiveIntervals>());
RegAllocBase::init(getAnalysis<VirtRegMap>(), getAnalysis<LiveIntervals>());
ReservedRegs = TRI->getReservedRegs(*MF);

15
lib/CodeGen/RegAllocGreedy.cpp
View File

@ -45,9 +45,6 @@ namespace {
class RAGreedy : public MachineFunctionPass, public RegAllocBase {
// context
MachineFunction *MF;
const TargetMachine *TM;
MachineRegisterInfo *MRI;
BitVector ReservedRegs;
// analyses
@ -230,11 +227,6 @@ unsigned RAGreedy::selectOrSplit(LiveInterval &VirtReg,
SmallVector<unsigned, 8> PhysRegSpillCands, ReassignCands;
// Check for an available register in this class.
DEBUG({
const TargetRegisterClass *TRC = MRI->getRegClass(VirtReg.reg);
dbgs() << "RegClass: " << TRC->getName() << ' ';
});
AllocationOrder Order(VirtReg.reg, *VRM, ReservedRegs);
while (unsigned PhysReg = Order.next()) {
// Check interference and as a side effect, intialize queries for this
@ -305,12 +297,7 @@ bool RAGreedy::runOnMachineFunction(MachineFunction &mf) {
<< ((Value*)mf.getFunction())->getName() << '\n');
MF = &mf;
TM = &mf.getTarget();
MRI = &mf.getRegInfo();
const TargetRegisterInfo *TRI = TM->getRegisterInfo();
RegAllocBase::init(*TRI, getAnalysis<VirtRegMap>(),
getAnalysis<LiveIntervals>());
RegAllocBase::init(getAnalysis<VirtRegMap>(), getAnalysis<LiveIntervals>());
ReservedRegs = TRI->getReservedRegs(*MF);
SpillerInstance.reset(createInlineSpiller(*this, *MF, *VRM));