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[x86] Fix an embarressing bug in the INSERTPS formation code. The mask

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computation was totally wrong, but somehow it didn't really show up with
llc.

I've added an assert that triggers on multiple existing test cases and
updated one of them to show the correct value.

There appear to still be more bugs lurking around insertps's mask. =/
However, note that this only really impacts the new vector shuffle
lowering.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217289 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chandler Carruth 2014-09-05 23:19:45 +00:00
parent cbbae7f41d
commit 469c73bc27
2 changed files with 5 additions and 4 deletions
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7
lib/Target/X86/X86ISelLowering.cpp
View File

@ -7417,11 +7417,12 @@ static SDValue lowerV4F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
if ((ZMask | 1 << V2Index) == 0xF) if ((ZMask | 1 << V2Index) == 0xF)
V1 = DAG.getUNDEF(MVT::v4f32); V1 = DAG.getUNDEF(MVT::v4f32);
unsigned InsertPSMask = (Mask[V2Index] - 4) << 6 | V2Index << 4 | ZMask;
assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
// Insert the V2 element into the desired position. // Insert the V2 element into the desired position.
SDValue InsertPSMask =
DAG.getIntPtrConstant(Mask[V2Index] << 6 | V2Index << 4 | ZMask);
return DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2, return DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
InsertPSMask); DAG.getConstant(InsertPSMask, MVT::i8));
} }
} }

2
test/CodeGen/X86/vec_set-3.ll
View File

@ -8,7 +8,7 @@ define <4 x float> @test(float %a) {
; CHECK-NEXT: retl ; CHECK-NEXT: retl
; ;
; CHECK-EXP-LABEL: test: ; CHECK-EXP-LABEL: test:
; CHECK-EXP: insertps $285, {{.*}}, %xmm0 ; CHECK-EXP: insertps $29, {{.*}}, %xmm0
; CHECK-EXP-NEXT: retl ; CHECK-EXP-NEXT: retl
entry: entry: