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Fix up the AssertXext problem, as well as adding it at calls

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23246 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Andrew Lenharth 2005-09-06 17:00:23 +00:00
parent 92cce90c66
commit 46a776e664
2 changed files with 25 additions and 14 deletions
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24
lib/Target/Alpha/AlphaISelLowering.cpp
View File

@ -135,8 +135,6 @@ AlphaTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG)
Alpha::R16, Alpha::R17, Alpha::R18, Alpha::R19, Alpha::R20, Alpha::R21};
unsigned args_float[] = {
Alpha::F16, Alpha::F17, Alpha::F18, Alpha::F19, Alpha::F20, Alpha::F21};
unsigned added_int = 0;
unsigned added_fp = 0;
int count = 0;
@ -156,7 +154,6 @@ AlphaTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG)
case MVT::f64:
case MVT::f32:
args_float[count] = AddLiveIn(MF, args_float[count], getRegClassFor(VT));
added_fp |= (1 << count);
argt = DAG.getCopyFromReg(DAG.getRoot(), args_float[count], VT);
DAG.setRoot(argt.getValue(1));
break;
@ -166,7 +163,6 @@ AlphaTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG)
case MVT::i32:
case MVT::i64:
args_int[count] = AddLiveIn(MF, args_int[count], getRegClassFor(MVT::i64));
added_int |= (1 << count);
argt = DAG.getCopyFromReg(DAG.getRoot(), args_int[count], MVT::i64);
DAG.setRoot(argt.getValue(1));
if (VT != MVT::i64) {
@ -197,7 +193,7 @@ AlphaTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG)
VarArgsOffset = count * 8;
std::vector<SDOperand> LS;
for (int i = 0; i < 6; ++i) {
if (!(added_int & (1 << i)))
if (args_int[i] < 1024)
args_int[i] = AddLiveIn(MF, args_int[i], getRegClassFor(MVT::i64));
SDOperand argt = DAG.getCopyFromReg(DAG.getRoot(), args_int[i], MVT::i64);
int FI = MFI->CreateFixedObject(8, -8 * (6 - i));
@ -206,7 +202,7 @@ AlphaTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG)
LS.push_back(DAG.getNode(ISD::STORE, MVT::Other, DAG.getRoot(), argt,
SDFI, DAG.getSrcValue(NULL)));
if (!(added_fp & (1 << i)))
if (args_float[i] < 1024)
args_float[i] = AddLiveIn(MF, args_float[i], getRegClassFor(MVT::f64));
argt = DAG.getCopyFromReg(DAG.getRoot(), args_float[i], MVT::f64);
FI = MFI->CreateFixedObject(8, - 8 * (12 - i));
@ -278,8 +274,12 @@ AlphaTargetLowering::LowerCallTo(SDOperand Chain,
std::vector<MVT::ValueType> RetVals;
MVT::ValueType RetTyVT = getValueType(RetTy);
MVT::ValueType ActualRetTyVT = RetTyVT;
if (RetTyVT >= MVT::i1 && RetTyVT <= MVT::i32)
ActualRetTyVT = MVT::i64;
if (RetTyVT != MVT::isVoid)
RetVals.push_back(RetTyVT);
RetVals.push_back(ActualRetTyVT);
RetVals.push_back(MVT::Other);
SDOperand TheCall = SDOperand(DAG.getCall(RetVals,
@ -287,7 +287,15 @@ AlphaTargetLowering::LowerCallTo(SDOperand Chain,
Chain = TheCall.getValue(RetTyVT != MVT::isVoid);
Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain,
DAG.getConstant(NumBytes, getPointerTy()));
return std::make_pair(TheCall, Chain);
SDOperand RetVal = TheCall;
if (RetTyVT != ActualRetTyVT) {
RetVal = DAG.getNode(RetTy->isSigned() ? ISD::AssertSext : ISD::AssertZext,
MVT::i64, RetVal, DAG.getValueType(RetTyVT));
RetVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, RetVal);
}
return std::make_pair(RetVal, Chain);
}
SDOperand AlphaTargetLowering::LowerVAStart(SDOperand Chain, SDOperand VAListP,

15
lib/Target/Alpha/AlphaISelPattern.cpp
View File

@ -691,10 +691,16 @@ unsigned AlphaISel::SelectExpr(SDOperand N) {
unsigned &Reg = ExprMap[N];
if (Reg) return Reg;
if (N.getOpcode() != ISD::CALL && N.getOpcode() != ISD::TAILCALL)
switch(N.getOpcode()) {
default:
Reg = Result = (N.getValueType() != MVT::Other) ?
MakeReg(N.getValueType()) : notIn;
else {
break;
case ISD::AssertSext:
case ISD::AssertZext:
return Reg = SelectExpr(N.getOperand(0));
case ISD::CALL:
case ISD::TAILCALL:
// If this is a call instruction, make sure to prepare ALL of the result
// values as well as the chain.
if (Node->getNumValues() == 1)
@ -706,6 +712,7 @@ unsigned AlphaISel::SelectExpr(SDOperand N) {
ExprMap[N.getValue(i)] = MakeReg(Node->getValueType(i));
ExprMap[SDOperand(Node, Node->getNumValues()-1)] = notIn;
}
break;
}
switch (opcode) {
@ -1003,10 +1010,6 @@ unsigned AlphaISel::SelectExpr(SDOperand N) {
switch (Node->getValueType(0)) {
default: Node->dump(); assert(0 && "Unknown value type for call result!");
case MVT::Other: return notIn;
case MVT::i1:
case MVT::i8:
case MVT::i16:
case MVT::i32:
case MVT::i64:
BuildMI(BB, Alpha::BIS, 2, Result).addReg(Alpha::R0).addReg(Alpha::R0);
break;