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change the addressing mode of the str instruction to reg+imm
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29571 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -22,6 +22,10 @@ ARMInstrInfo::ARMInstrInfo()
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: TargetInstrInfo(ARMInsts, sizeof(ARMInsts)/sizeof(ARMInsts[0])) {
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}
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const TargetRegisterClass *ARMInstrInfo::getPointerRegClass() const {
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return &ARM::IntRegsRegClass;
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}
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/// Return true if the instruction is a register to register move and
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/// leave the source and dest operands in the passed parameters.
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///
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@ -31,6 +31,10 @@ public:
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///
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virtual const MRegisterInfo &getRegisterInfo() const { return RI; }
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/// getPointerRegClass - Return the register class to use to hold pointers.
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/// This is used for addressing modes.
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virtual const TargetRegisterClass *getPointerRegClass() const;
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/// Return true if the instruction is a register to register move and
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/// leave the source and dest operands in the passed parameters.
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///
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@ -67,9 +67,9 @@ def ldr : InstARM<(ops IntRegs:$dst, memri:$addr),
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"ldr $dst, $addr",
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[(set IntRegs:$dst, (load iaddr:$addr))]>;
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def str : InstARM<(ops IntRegs:$src, IntRegs:$addr),
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"str $src, [$addr]",
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[(store IntRegs:$src, IntRegs:$addr)]>;
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def str : InstARM<(ops IntRegs:$src, memri:$addr),
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"str $src, $addr",
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[(store IntRegs:$src, iaddr:$addr)]>;
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def movrr : InstARM<(ops IntRegs:$dst, IntRegs:$src),
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"mov $dst, $src", []>;
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@ -135,10 +135,8 @@ void ARMRegisterInfo::emitPrologue(MachineFunction &MF) const {
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//sub sp, sp, #NumBytes
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BuildMI(MBB, MBBI, ARM::subri, 2, ARM::R13).addReg(ARM::R13).addImm(NumBytes);
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//add ip, sp, #NumBytes - 4
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BuildMI(MBB, MBBI, ARM::addri, 2, ARM::R12).addReg(ARM::R13).addImm(NumBytes - 4);
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//str lr, [ip]
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BuildMI(MBB, MBBI, ARM::str, 1, ARM::R14).addReg(ARM::R12);
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//str lr, [sp, #NumBytes - 4]
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BuildMI(MBB, MBBI, ARM::str, 2, ARM::R14).addImm(NumBytes - 4).addReg(ARM::R13);
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}
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void ARMRegisterInfo::emitEpilogue(MachineFunction &MF,
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