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https://github.com/c64scene-ar/llvm-6502.git
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[AArch64 NEON] Fix generating incorrect value type of NEON_VDUPLANE
when lower build_vector if result value type mismatch with operand value type. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198743 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Kevin Qin
parent
8f5124903f
commit
4712264fb8
@ -4107,14 +4107,60 @@ AArch64TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
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// just use DUPLANE. We can only do this if the lane being extracted
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// is at a constant index, as the DUP from lane instructions only have
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// constant-index forms.
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//
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// If there is a TRUNCATE between EXTRACT_VECTOR_ELT and DUP, we can
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// remove TRUNCATE for DUPLANE by apdating the source vector to
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// appropriate vector type and lane index.
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//
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// FIXME: for now we have v1i8, v1i16, v1i32 legal vector types, if they
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// are not legal any more, no need to check the type size in bits should
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// be large than 64.
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if (Value->getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
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isa<ConstantSDNode>(Value->getOperand(1)) &&
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Value->getOperand(0).getValueType().getSizeInBits() >= 64) {
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N = DAG.getNode(AArch64ISD::NEON_VDUPLANE, DL, VT,
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Value->getOperand(0), Value->getOperand(1));
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SDValue V = Value;
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if (Value->getOpcode() == ISD::TRUNCATE)
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V = Value->getOperand(0);
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if (V->getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
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isa<ConstantSDNode>(V->getOperand(1)) &&
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V->getOperand(0).getValueType().getSizeInBits() >= 64) {
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// If the element size of source vector is larger than DUPLANE
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// element size, we can do transformation by,
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// 1) bitcasting source register to smaller element vector
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// 2) mutiplying the lane index by SrcEltSize/ResEltSize
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// For example, we can lower
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// "v8i16 vdup_lane(v4i32, 1)"
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// to be
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// "v8i16 vdup_lane(v8i16 bitcast(v4i32), 2)".
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SDValue SrcVec = V->getOperand(0);
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unsigned SrcEltSize =
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SrcVec.getValueType().getVectorElementType().getSizeInBits();
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unsigned ResEltSize = VT.getVectorElementType().getSizeInBits();
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if (SrcEltSize > ResEltSize) {
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assert((SrcEltSize % ResEltSize == 0) && "Invalid element size");
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SDValue BitCast;
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unsigned SrcSize = SrcVec.getValueType().getSizeInBits();
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unsigned ResSize = VT.getSizeInBits();
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if (SrcSize > ResSize) {
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assert((SrcSize % ResSize == 0) && "Invalid vector size");
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EVT CastVT =
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EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(),
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SrcSize / ResEltSize);
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BitCast = DAG.getNode(ISD::BITCAST, DL, CastVT, SrcVec);
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} else {
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assert((SrcSize == ResSize) && "Invalid vector size of source vec");
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BitCast = DAG.getNode(ISD::BITCAST, DL, VT, SrcVec);
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}
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unsigned LaneIdx = V->getConstantOperandVal(1);
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SDValue Lane =
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DAG.getConstant((SrcEltSize / ResEltSize) * LaneIdx, MVT::i64);
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N = DAG.getNode(AArch64ISD::NEON_VDUPLANE, DL, VT, BitCast, Lane);
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} else {
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assert((SrcEltSize == ResEltSize) &&
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"Invalid element size of source vec");
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N = DAG.getNode(AArch64ISD::NEON_VDUPLANE, DL, VT, V->getOperand(0),
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V->getOperand(1));
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}
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} else
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N = DAG.getNode(AArch64ISD::NEON_VDUP, DL, VT, Value);
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@ -726,3 +726,125 @@ define <8 x i8> @getl(<16 x i8> %x) #0 {
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%vecinit14 = insertelement <8 x i8> %vecinit12, i8 %vecext13, i32 7
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ret <8 x i8> %vecinit14
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}
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define <4 x i16> @test_dup_v2i32_v4i16(<2 x i32> %a) {
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; CHECK-LABEL: test_dup_v2i32_v4i16:
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; CHECK: dup v0.4h, v0.h[2]
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entry:
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%x = extractelement <2 x i32> %a, i32 1
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%vget_lane = trunc i32 %x to i16
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%vecinit.i = insertelement <4 x i16> undef, i16 %vget_lane, i32 0
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%vecinit1.i = insertelement <4 x i16> %vecinit.i, i16 %vget_lane, i32 1
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%vecinit2.i = insertelement <4 x i16> %vecinit1.i, i16 %vget_lane, i32 2
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%vecinit3.i = insertelement <4 x i16> %vecinit2.i, i16 %vget_lane, i32 3
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ret <4 x i16> %vecinit3.i
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}
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define <8 x i16> @test_dup_v4i32_v8i16(<4 x i32> %a) {
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; CHECK-LABEL: test_dup_v4i32_v8i16:
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; CHECK: dup v0.8h, v0.h[6]
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entry:
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%x = extractelement <4 x i32> %a, i32 3
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%vget_lane = trunc i32 %x to i16
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%vecinit.i = insertelement <8 x i16> undef, i16 %vget_lane, i32 0
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%vecinit1.i = insertelement <8 x i16> %vecinit.i, i16 %vget_lane, i32 1
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%vecinit2.i = insertelement <8 x i16> %vecinit1.i, i16 %vget_lane, i32 2
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%vecinit3.i = insertelement <8 x i16> %vecinit2.i, i16 %vget_lane, i32 3
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%vecinit4.i = insertelement <8 x i16> %vecinit3.i, i16 %vget_lane, i32 4
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%vecinit5.i = insertelement <8 x i16> %vecinit4.i, i16 %vget_lane, i32 5
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%vecinit6.i = insertelement <8 x i16> %vecinit5.i, i16 %vget_lane, i32 6
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%vecinit7.i = insertelement <8 x i16> %vecinit6.i, i16 %vget_lane, i32 7
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ret <8 x i16> %vecinit7.i
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}
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define <4 x i16> @test_dup_v1i64_v4i16(<1 x i64> %a) {
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; CHECK-LABEL: test_dup_v1i64_v4i16:
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; CHECK: dup v0.4h, v0.h[0]
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entry:
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%x = extractelement <1 x i64> %a, i32 0
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%vget_lane = trunc i64 %x to i16
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%vecinit.i = insertelement <4 x i16> undef, i16 %vget_lane, i32 0
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%vecinit1.i = insertelement <4 x i16> %vecinit.i, i16 %vget_lane, i32 1
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%vecinit2.i = insertelement <4 x i16> %vecinit1.i, i16 %vget_lane, i32 2
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%vecinit3.i = insertelement <4 x i16> %vecinit2.i, i16 %vget_lane, i32 3
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ret <4 x i16> %vecinit3.i
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}
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define <2 x i32> @test_dup_v1i64_v2i32(<1 x i64> %a) {
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; CHECK-LABEL: test_dup_v1i64_v2i32:
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; CHECK: dup v0.2s, v0.s[0]
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entry:
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%x = extractelement <1 x i64> %a, i32 0
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%vget_lane = trunc i64 %x to i32
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%vecinit.i = insertelement <2 x i32> undef, i32 %vget_lane, i32 0
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%vecinit1.i = insertelement <2 x i32> %vecinit.i, i32 %vget_lane, i32 1
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ret <2 x i32> %vecinit1.i
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}
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define <8 x i16> @test_dup_v2i64_v8i16(<2 x i64> %a) {
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; CHECK-LABEL: test_dup_v2i64_v8i16:
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; CHECK: dup v0.8h, v0.h[4]
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entry:
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%x = extractelement <2 x i64> %a, i32 1
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%vget_lane = trunc i64 %x to i16
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%vecinit.i = insertelement <8 x i16> undef, i16 %vget_lane, i32 0
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%vecinit1.i = insertelement <8 x i16> %vecinit.i, i16 %vget_lane, i32 1
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%vecinit2.i = insertelement <8 x i16> %vecinit1.i, i16 %vget_lane, i32 2
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%vecinit3.i = insertelement <8 x i16> %vecinit2.i, i16 %vget_lane, i32 3
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%vecinit4.i = insertelement <8 x i16> %vecinit3.i, i16 %vget_lane, i32 4
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%vecinit5.i = insertelement <8 x i16> %vecinit4.i, i16 %vget_lane, i32 5
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%vecinit6.i = insertelement <8 x i16> %vecinit5.i, i16 %vget_lane, i32 6
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%vecinit7.i = insertelement <8 x i16> %vecinit6.i, i16 %vget_lane, i32 7
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ret <8 x i16> %vecinit7.i
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}
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define <4 x i32> @test_dup_v2i64_v4i32(<2 x i64> %a) {
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; CHECK-LABEL: test_dup_v2i64_v4i32:
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; CHECK: dup v0.4s, v0.s[2]
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entry:
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%x = extractelement <2 x i64> %a, i32 1
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%vget_lane = trunc i64 %x to i32
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%vecinit.i = insertelement <4 x i32> undef, i32 %vget_lane, i32 0
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%vecinit1.i = insertelement <4 x i32> %vecinit.i, i32 %vget_lane, i32 1
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%vecinit2.i = insertelement <4 x i32> %vecinit1.i, i32 %vget_lane, i32 2
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%vecinit3.i = insertelement <4 x i32> %vecinit2.i, i32 %vget_lane, i32 3
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ret <4 x i32> %vecinit3.i
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}
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define <4 x i16> @test_dup_v4i32_v4i16(<4 x i32> %a) {
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; CHECK-LABEL: test_dup_v4i32_v4i16:
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; CHECK: dup v0.4h, v0.h[2]
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entry:
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%x = extractelement <4 x i32> %a, i32 1
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%vget_lane = trunc i32 %x to i16
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%vecinit.i = insertelement <4 x i16> undef, i16 %vget_lane, i32 0
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%vecinit1.i = insertelement <4 x i16> %vecinit.i, i16 %vget_lane, i32 1
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%vecinit2.i = insertelement <4 x i16> %vecinit1.i, i16 %vget_lane, i32 2
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%vecinit3.i = insertelement <4 x i16> %vecinit2.i, i16 %vget_lane, i32 3
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ret <4 x i16> %vecinit3.i
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}
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define <4 x i16> @test_dup_v2i64_v4i16(<2 x i64> %a) {
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; CHECK-LABEL: test_dup_v2i64_v4i16:
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; CHECK: dup v0.4h, v0.h[0]
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entry:
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%x = extractelement <2 x i64> %a, i32 0
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%vget_lane = trunc i64 %x to i16
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%vecinit.i = insertelement <4 x i16> undef, i16 %vget_lane, i32 0
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%vecinit1.i = insertelement <4 x i16> %vecinit.i, i16 %vget_lane, i32 1
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%vecinit2.i = insertelement <4 x i16> %vecinit1.i, i16 %vget_lane, i32 2
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%vecinit3.i = insertelement <4 x i16> %vecinit2.i, i16 %vget_lane, i32 3
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ret <4 x i16> %vecinit3.i
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}
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define <2 x i32> @test_dup_v2i64_v2i32(<2 x i64> %a) {
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; CHECK-LABEL: test_dup_v2i64_v2i32:
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; CHECK: dup v0.2s, v0.s[0]
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entry:
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%x = extractelement <2 x i64> %a, i32 0
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%vget_lane = trunc i64 %x to i32
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%vecinit.i = insertelement <2 x i32> undef, i32 %vget_lane, i32 0
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%vecinit1.i = insertelement <2 x i32> %vecinit.i, i32 %vget_lane, i32 1
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ret <2 x i32> %vecinit1.i
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}
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