[ARM] Fix Tag_ABI_HardFP_use build attribute

Fix Tag_ABI_HardFP_use build attribute to handle single precision FP,
replace deprecated Tag_ABI_HardFP_use value of 3 with 0 and also add
some tests for Tag_ABI_VFP_args.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193856 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/ARM/ARMAsmPrinter.cpp

@@ -692,11 +692,15 @@ void ARMAsmPrinter::emitAttributes() {
   ATS.emitAttribute(ARMBuildAttrs::ABI_align8_needed, 1);
   ATS.emitAttribute(ARMBuildAttrs::ABI_align8_preserved, 1);
 
+  // ABI_HardFP_use attribute to indicate single precision FP.
+  if (Subtarget->isFPOnlySP())
+    ATS.emitAttribute(ARMBuildAttrs::ABI_HardFP_use,
+                      ARMBuildAttrs::HardFPSinglePrecision);
+
   // Hard float.  Use both S and D registers and conform to AAPCS-VFP.
-  if (Subtarget->isAAPCS_ABI() && TM.Options.FloatABIType == FloatABI::Hard) {
+  if (Subtarget->isAAPCS_ABI() && TM.Options.FloatABIType == FloatABI::Hard)
-    ATS.emitAttribute(ARMBuildAttrs::ABI_HardFP_use, 3);
+    ATS.emitAttribute(ARMBuildAttrs::ABI_VFP_args, ARMBuildAttrs::HardFPAAPCS);
-    ATS.emitAttribute(ARMBuildAttrs::ABI_VFP_args, 1);
+
-  }
   // FIXME: Should we signal R9 usage?
 
   if (Subtarget->hasDivide()) {

lib/Target/ARM/ARMBuildAttrs.h

@@ -137,8 +137,12 @@ namespace ARMBuildAttrs {
     AllowIEE754 = 3, // this code to use all the IEEE 754-defined FP encodings
 
     // Tag_ABI_HardFP_use, (=27), uleb128
+    HardFPImplied = 0, // FP use should be implied by Tag_FP_arch
     HardFPSinglePrecision = 1, // Single-precision only
-    HardFPImplied = 3, // FP use should be implied by Tag_FP_arch
+
+    // Tag_ABI_VFP_args, (=28), uleb128
+    BaseAAPCS = 0,
+    HardFPAAPCS = 1,
 
     // Tag_DIV_use, (=44), uleb128
     AllowDIVIfExists = 0, // Allow hardware divide if available in arch, or no info exists.

test/CodeGen/ARM/2010-09-29-mc-asm-header-test.ll

@@ -12,10 +12,12 @@
 ; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mattr=-fp-armv8,-crypto | FileCheck %s --check-prefix=V8-NEON
 ; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mattr=-crypto | FileCheck %s --check-prefix=V8-FPARMv8-NEON
 ; RUN: llc < %s -mtriple=armv8-linux-gnueabi | FileCheck %s --check-prefix=V8-FPARMv8-NEON-CRYPTO
-; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a9 | FileCheck %s --check-prefix=CORTEX-A9
+; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a9 -float-abi=soft | FileCheck %s --check-prefix=CORTEX-A9-SOFT
+; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a9 -float-abi=hard | FileCheck %s --check-prefix=CORTEX-A9-HARD
 ; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a15 | FileCheck %s --check-prefix=CORTEX-A15
 ; RUN: llc < %s -mtriple=thumbv6m-linux-gnueabi -mcpu=cortex-m0 | FileCheck %s --check-prefix=CORTEX-M0
-; RUN: llc < %s -mtriple=thumbv7m-linux-gnueabi -mcpu=cortex-m4 | FileCheck %s --check-prefix=CORTEX-M4
+; RUN: llc < %s -mtriple=thumbv7m-linux-gnueabi -mcpu=cortex-m4 -float-abi=soft | FileCheck %s --check-prefix=CORTEX-M4-SOFT
+; RUN: llc < %s -mtriple=thumbv7m-linux-gnueabi -mcpu=cortex-m4 -float-abi=hard | FileCheck %s --check-prefix=CORTEX-M4-HARD
 ; RUN: llc < %s -mtriple=armv7r-linux-gnueabi -mcpu=cortex-r5 | FileCheck %s --check-prefix=CORTEX-R5
 ; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mcpu=cortex-a53 | FileCheck %s --check-prefix=CORTEX-A53
 ; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mcpu=cortex-a57 | FileCheck %s --check-prefix=CORTEX-A57
@@ -24,6 +26,8 @@
 ; V6:   .eabi_attribute 8, 1
 ; V6:   .eabi_attribute 24, 1
 ; V6:   .eabi_attribute 25, 1
+; V6-NOT:   .eabi_attribute 27
+; V6-NOT:   .eabi_attribute 28
 
 ; V6M:  .eabi_attribute 6, 12
 ; V6M:  .eabi_attribute 7, 77
@@ -31,6 +35,8 @@
 ; V6M:  .eabi_attribute 9, 1
 ; V6M:  .eabi_attribute 24, 1
 ; V6M:  .eabi_attribute 25, 1
+; V6M-NOT:  .eabi_attribute 27
+; V6M-NOT:  .eabi_attribute 28
 
 ; ARM1156T2F-S: .cpu arm1156t2f-s
 ; ARM1156T2F-S: .eabi_attribute 6, 8
@@ -42,6 +48,8 @@
 ; ARM1156T2F-S: .eabi_attribute 23, 3
 ; ARM1156T2F-S: .eabi_attribute 24, 1
 ; ARM1156T2F-S: .eabi_attribute 25, 1
+; ARM1156T2F-S-NOT: .eabi_attribute 27
+; ARM1156T2F-S-NOT: .eabi_attribute 28
 
 ; V7M:  .eabi_attribute 6, 10
 ; V7M:  .eabi_attribute 7, 77
@@ -49,6 +57,8 @@
 ; V7M:  .eabi_attribute 9, 2
 ; V7M:  .eabi_attribute 24, 1
 ; V7M:  .eabi_attribute 25, 1
+; V7M-NOT:  .eabi_attribute 27
+; V7M-NOT:  .eabi_attribute 28
 ; V7M:  .eabi_attribute 44, 0
 
 ; V7:      .syntax unified
@@ -58,6 +68,8 @@
 ; V7: .eabi_attribute 23, 3
 ; V7: .eabi_attribute 24, 1
 ; V7: .eabi_attribute 25, 1
+; V7-NOT: .eabi_attribute 27
+; V7-NOT: .eabi_attribute 28
 
 ; V8:      .syntax unified
 ; V8: .eabi_attribute 6, 14
@@ -84,17 +96,33 @@
 ; V8-FPARMv8-NEON-CRYPTO: .fpu crypto-neon-fp-armv8
 ; V8-FPARMv8-NEON-CRYPTO: .eabi_attribute 12, 3
 
-; CORTEX-A9:  .cpu cortex-a9
+; CORTEX-A9-SOFT:  .cpu cortex-a9
-; CORTEX-A9:  .eabi_attribute 6, 10
+; CORTEX-A9-SOFT:  .eabi_attribute 6, 10
-; CORTEX-A9:  .eabi_attribute 7, 65
+; CORTEX-A9-SOFT:  .eabi_attribute 7, 65
-; CORTEX-A9:  .eabi_attribute 8, 1
+; CORTEX-A9-SOFT:  .eabi_attribute 8, 1
-; CORTEX-A9:  .eabi_attribute 9, 2
+; CORTEX-A9-SOFT:  .eabi_attribute 9, 2
-; CORTEX-A9:  .fpu neon
+; CORTEX-A9-SOFT:  .fpu neon
-; CORTEX-A9:  .eabi_attribute 20, 1
+; CORTEX-A9-SOFT:  .eabi_attribute 20, 1
-; CORTEX-A9:  .eabi_attribute 21, 1
+; CORTEX-A9-SOFT:  .eabi_attribute 21, 1
-; CORTEX-A9:  .eabi_attribute 23, 3
+; CORTEX-A9-SOFT:  .eabi_attribute 23, 3
-; CORTEX-A9:  .eabi_attribute 24, 1
+; CORTEX-A9-SOFT:  .eabi_attribute 24, 1
-; CORTEX-A9:  .eabi_attribute 25, 1
+; CORTEX-A9-SOFT:  .eabi_attribute 25, 1
+; CORTEX-A9-SOFT-NOT:  .eabi_attribute 27
+; CORTEX-A9-SOFT-NOT:  .eabi_attribute 28
+
+; CORTEX-A9-HARD:  .cpu cortex-a9
+; CORTEX-A9-HARD:  .eabi_attribute 6, 10
+; CORTEX-A9-HARD:  .eabi_attribute 7, 65
+; CORTEX-A9-HARD:  .eabi_attribute 8, 1
+; CORTEX-A9-HARD:  .eabi_attribute 9, 2
+; CORTEX-A9-HARD:  .fpu neon
+; CORTEX-A9-HARD:  .eabi_attribute 20, 1
+; CORTEX-A9-HARD:  .eabi_attribute 21, 1
+; CORTEX-A9-HARD:  .eabi_attribute 23, 3
+; CORTEX-A9-HARD:  .eabi_attribute 24, 1
+; CORTEX-A9-HARD:  .eabi_attribute 25, 1
+; CORTEX-A9-HARD-NOT:  .eabi_attribute 27
+; CORTEX-A9-HARD:  .eabi_attribute 28, 1
 
 ; CORTEX-A15: .cpu cortex-a15
 ; CORTEX-A15: .eabi_attribute 6, 10
@@ -108,6 +136,8 @@
 ; CORTEX-A15: .eabi_attribute 24, 1
 ; CORTEX-A15: .eabi_attribute 25, 1
 ; CORTEX-A15: .eabi_attribute 44, 2
+; CORTEX-A15-NOT: .eabi_attribute 27
+; CORTEX-A15-NOT: .eabi_attribute 28
 
 ; CORTEX-M0:  .cpu cortex-m0
 ; CORTEX-M0:  .eabi_attribute 6, 12
@@ -116,19 +146,38 @@
 ; CORTEX-M0:  .eabi_attribute 9, 1
 ; CORTEX-M0:  .eabi_attribute 24, 1
 ; CORTEX-M0:  .eabi_attribute 25, 1
+; CORTEX-M0-NOT:  .eabi_attribute 27
+; CORTEX-M0-NOT:  .eabi_attribute 28
 
-; CORTEX-M4:  .cpu cortex-m4
+; CORTEX-M4-SOFT:  .cpu cortex-m4
-; CORTEX-M4:  .eabi_attribute 6, 13
+; CORTEX-M4-SOFT:  .eabi_attribute 6, 13
-; CORTEX-M4:  .eabi_attribute 7, 77
+; CORTEX-M4-SOFT:  .eabi_attribute 7, 77
-; CORTEX-M4:  .eabi_attribute 8, 0
+; CORTEX-M4-SOFT:  .eabi_attribute 8, 0
-; CORTEX-M4:  .eabi_attribute 9, 2
+; CORTEX-M4-SOFT:  .eabi_attribute 9, 2
-; CORTEX-M4:  .fpu vfpv4-d16
+; CORTEX-M4-SOFT:  .fpu vfpv4-d16
-; CORTEX-M4:  .eabi_attribute 20, 1
+; CORTEX-M4-SOFT:  .eabi_attribute 20, 1
-; CORTEX-M4:  .eabi_attribute 21, 1
+; CORTEX-M4-SOFT:  .eabi_attribute 21, 1
-; CORTEX-M4:  .eabi_attribute 23, 3
+; CORTEX-M4-SOFT:  .eabi_attribute 23, 3
-; CORTEX-M4:  .eabi_attribute 24, 1
+; CORTEX-M4-SOFT:  .eabi_attribute 24, 1
-; CORTEX-M4:  .eabi_attribute 25, 1
+; CORTEX-M4-SOFT:  .eabi_attribute 25, 1
-; CORTEX-M4:  .eabi_attribute 44, 0
+; CORTEX-M4-SOFT:  .eabi_attribute 27, 1
+; CORTEX-M4-SOFT-NOT:  .eabi_attribute 28
+; CORTEX-M4-SOFT:  .eabi_attribute 44, 0
+
+; CORTEX-M4-HARD:  .cpu cortex-m4
+; CORTEX-M4-HARD:  .eabi_attribute 6, 13
+; CORTEX-M4-HARD:  .eabi_attribute 7, 77
+; CORTEX-M4-HARD:  .eabi_attribute 8, 0
+; CORTEX-M4-HARD:  .eabi_attribute 9, 2
+; CORTEX-M4-HARD:  .fpu vfpv4-d16
+; CORTEX-M4-HARD:  .eabi_attribute 20, 1
+; CORTEX-M4-HARD:  .eabi_attribute 21, 1
+; CORTEX-M4-HARD:  .eabi_attribute 23, 3
+; CORTEX-M4-HARD:  .eabi_attribute 24, 1
+; CORTEX-M4-HARD:  .eabi_attribute 25, 1
+; CORTEX-M4-HARD:  .eabi_attribute 27, 1
+; CORTEX-M4-HARD:  .eabi_attribute 28, 1
+; CORTEX-M4-HARD:  .eabi_attribute 44, 0
 
 ; CORTEX-R5:  .cpu cortex-r5
 ; CORTEX-R5:  .eabi_attribute 6, 10
@@ -141,6 +190,8 @@
 ; CORTEX-R5:  .eabi_attribute 23, 3
 ; CORTEX-R5:  .eabi_attribute 24, 1
 ; CORTEX-R5:  .eabi_attribute 25, 1
+; CORTEX-R5:  .eabi_attribute 27, 1
+; CORTEX-R5-NOT:  .eabi_attribute 28
 ; CORTEX-R5:  .eabi_attribute 44, 2
 
 ; CORTEX-A53:  .cpu cortex-a53
@@ -152,6 +203,8 @@
 ; CORTEX-A53:  .eabi_attribute 12, 3
 ; CORTEX-A53:  .eabi_attribute 24, 1
 ; CORTEX-A53:  .eabi_attribute 25, 1
+; CORTEX-A53-NOT:  .eabi_attribute 27
+; CORTEX-A53-NOT:  .eabi_attribute 28
 ; CORTEX-A53:  .eabi_attribute 44, 2
 
 ; CORTEX-A57:  .cpu cortex-a57
@@ -163,6 +216,8 @@
 ; CORTEX-A57:  .eabi_attribute 12, 3
 ; CORTEX-A57:  .eabi_attribute 24, 1
 ; CORTEX-A57:  .eabi_attribute 25, 1
+; CORTEX-A57-NOT:  .eabi_attribute 27
+; CORTEX-A57-NOT:  .eabi_attribute 28
 ; CORTEX-A57:  .eabi_attribute 44, 2
 
 define i32 @f(i64 %z) {

test/CodeGen/ARM/2010-10-19-mc-elf-objheader.ll

@@ -228,16 +228,16 @@
 ; CORTEX-M4-NEXT: ]
 ; CORTEX-M4-NEXT: Address: 0x0
 ; CORTEX-M4-NEXT: Offset: 0x38
-; CORTEX-M4-NEXT: Size: 49
+; CORTEX-M4-NEXT: Size: 51
 ; CORTEX-M4-NEXT: Link: 0
 ; CORTEX-M4-NEXT: Info: 0
 ; CORTEX-M4-NEXT: AddressAlignment: 1
 ; CORTEX-M4-NEXT: EntrySize: 0
 ; CORTEX-M4-NEXT: SectionData (
-; CORTEX-M4-NEXT:   0000: 41300000 00616561 62690001 26000000
+; CORTEX-M4-NEXT:   0000: 41320000 00616561 62690001 28000000
 ; CORTEX-M4-NEXT:   0010: 05434F52 5445582D 4D340006 0D074D08
-; CORTEX-M4-NEXT:   0020: 0009020A 06140115 01170318 0119012C
+; CORTEX-M4-NEXT:   0020: 0009020A 06140115 01170318 0119011B
-; CORTEX-M4-NEXT:   0030: 00
+; CORTEX-M4-NEXT:   0030: 012C00
 ; CORTEX-M4-NEXT: )
 
 ; CORTEX-R5:      Name: .ARM.attributes
@@ -246,16 +246,16 @@
 ; CORTEX-R5-NEXT: ]
 ; CORTEX-R5-NEXT: Address: 0x0
 ; CORTEX-R5-NEXT: Offset: 0x3C
-; CORTEX-R5-NEXT: Size: 49
+; CORTEX-R5-NEXT: Size: 51
 ; CORTEX-R5-NEXT: Link: 0
 ; CORTEX-R5-NEXT: Info: 0
 ; CORTEX-R5-NEXT: AddressAlignment: 1
 ; CORTEX-R5-NEXT: EntrySize: 0
 ; CORTEX-R5-NEXT: SectionData (
-; CORTEX-R5-NEXT:   0000: 41300000 00616561 62690001 26000000
+; CORTEX-R5-NEXT:   0000: 41320000 00616561 62690001 28000000
 ; CORTEX-R5-NEXT:   0010: 05434F52 5445582D 52350006 0A075208
-; CORTEX-R5-NEXT:   0020: 0109020A 04140115 01170318 0119012C
+; CORTEX-R5-NEXT:   0020: 0109020A 04140115 01170318 0119011B
-; CORTEX-R5-NEXT:   0030: 02
+; CORTEX-R5-NEXT:   0030: 012C02
 ; CORTEX-R5-NEXT: )
 
 define i32 @f(i64 %z) {