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[X86][Haswell][SchedModel] Add architecture specific scheduling models.

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Group: Floating Point XMM and YMM instructions.
Sub-group: Other instructions.

<rdar://problem/15607571>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215923 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Quentin Colombet 2014-08-18 17:55:59 +00:00
parent 7af88ec907
commit 48e3a273de
1 changed files with 30 additions and 0 deletions
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30
lib/Target/X86/X86SchedHaswell.td
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@ -2106,4 +2106,34 @@ def : InstRW<[WriteP5], (instregex "(V?)(AND|ANDN|OR|XOR)P(S|D)(Y?)rr")>;
def : InstRW<[WriteP5Ld, ReadAfterLd],
(instregex "(V?)(AND|ANDN|OR|XOR)P(S|D)(Y?)rm")>;
//-- Other instructions --//
// VZEROUPPER.
def WriteVZEROUPPER : SchedWriteRes<[]> {
let NumMicroOps = 4;
}
def : InstRW<[WriteVZEROUPPER], (instregex "VZEROUPPER")>;
// VZEROALL.
def WriteVZEROALL : SchedWriteRes<[]> {
let NumMicroOps = 12;
}
def : InstRW<[WriteVZEROALL], (instregex "VZEROALL")>;
// LDMXCSR.
def WriteLDMXCSR : SchedWriteRes<[HWPort0, HWPort6, HWPort23]> {
let Latency = 6;
let NumMicroOps = 3;
let ResourceCycles = [1, 1, 1];
}
def : InstRW<[WriteLDMXCSR], (instregex "(V)?LDMXCSR")>;
// STMXCSR.
def WriteSTMXCSR : SchedWriteRes<[HWPort0, HWPort4, HWPort6, HWPort237]> {
let Latency = 7;
let NumMicroOps = 4;
let ResourceCycles = [1, 1, 1, 1];
}
def : InstRW<[WriteSTMXCSR], (instregex "(V)?STMXCSR")>;
} // SchedModel