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[X86][Haswell][SchedModel] Add architecture specific scheduling models.

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Group: Floating Point XMM and YMM instructions.
Sub-group: Logic instructions.

<rdar://problem/15607571>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215922 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Quentin Colombet 2014-08-18 17:55:56 +00:00
parent 487ecab8d4
commit 7af88ec907
1 changed files with 9 additions and 0 deletions
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9
lib/Target/X86/X86SchedHaswell.td
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@ -2097,4 +2097,13 @@ def WriteRSQRTPSYm : SchedWriteRes<[HWPort0, HWPort15, HWPort23]> {
}
def : InstRW<[WriteRSQRTPSYm], (instregex "VRSQRTPSYm(_Int)?")>;
//-- Logic instructions --//
// AND, ANDN, OR, XOR PS/PD.
// x,x / v,v,v.
def : InstRW<[WriteP5], (instregex "(V?)(AND|ANDN|OR|XOR)P(S|D)(Y?)rr")>;
// x,m / v,v,m.
def : InstRW<[WriteP5Ld, ReadAfterLd],
(instregex "(V?)(AND|ANDN|OR|XOR)P(S|D)(Y?)rm")>;
} // SchedModel