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Replace SDT_PPCShiftOp in favor of SDTIntBinOps. This allows it to work
with 32 or 64-bit operands/results. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48026 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -20,9 +20,6 @@ include "PPCInstrFormats.td"
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def SDT_PPCstfiwx : SDTypeProfile<0, 2, [ // stfiwx
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def SDT_PPCstfiwx : SDTypeProfile<0, 2, [ // stfiwx
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SDTCisVT<0, f64>, SDTCisPtrTy<1>
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SDTCisVT<0, f64>, SDTCisPtrTy<1>
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]>;
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]>;
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def SDT_PPCShiftOp : SDTypeProfile<1, 2, [ // PPCshl, PPCsra, PPCsrl
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SDTCisVT<0, i32>, SDTCisVT<1, i32>, SDTCisVT<2, i32>
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]>;
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def SDT_PPCCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
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def SDT_PPCCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
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def SDT_PPCCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
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def SDT_PPCCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
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SDTCisVT<1, i32> ]>;
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SDTCisVT<1, i32> ]>;
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@ -84,9 +81,9 @@ def PPCvperm : SDNode<"PPCISD::VPERM", SDT_PPCvperm, []>;
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// These nodes represent the 32-bit PPC shifts that operate on 6-bit shift
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// These nodes represent the 32-bit PPC shifts that operate on 6-bit shift
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// amounts. These nodes are generated by the multi-precision shift code.
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// amounts. These nodes are generated by the multi-precision shift code.
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def PPCsrl : SDNode<"PPCISD::SRL" , SDT_PPCShiftOp>;
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def PPCsrl : SDNode<"PPCISD::SRL" , SDTIntBinOp>;
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def PPCsra : SDNode<"PPCISD::SRA" , SDT_PPCShiftOp>;
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def PPCsra : SDNode<"PPCISD::SRA" , SDTIntBinOp>;
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def PPCshl : SDNode<"PPCISD::SHL" , SDT_PPCShiftOp>;
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def PPCshl : SDNode<"PPCISD::SHL" , SDTIntBinOp>;
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def PPCextsw_32 : SDNode<"PPCISD::EXTSW_32" , SDTIntUnaryOp>;
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def PPCextsw_32 : SDNode<"PPCISD::EXTSW_32" , SDTIntUnaryOp>;
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def PPCstd_32 : SDNode<"PPCISD::STD_32" , SDTStore,
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def PPCstd_32 : SDNode<"PPCISD::STD_32" , SDTStore,
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