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Make g5 target explicit; scheduling affects register choice.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96413 91177308-0d34-0410-b5e6-96231b3b80d8
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Dale Johannesen 2010-02-16 23:25:23 +00:00
parent 53a2f60062
commit 4a12de72b0
1 changed files with 1 additions and 1 deletions
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test/CodeGen/PowerPC/2009-08-17-inline-asm-addr-mode-breakage.ll
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@ -1,4 +1,4 @@
; RUN: llc < %s -march=ppc32 | FileCheck %s
; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin10 -mcpu=g5 | FileCheck %s
; ModuleID = '<stdin>'
target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128"
target triple = "powerpc-apple-darwin10.0"