mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-10-01 10:57:21 +00:00
Rename many of the Tmp1, Tmp2, Tmp3 variables to names such as Chain, Value, Ptr, etc.
No functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160042 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Nadav Rotem
parent
a67306d21f
commit
4b24bf8da3
@ -642,9 +642,8 @@ SDValue SelectionDAGLegalize::OptimizeFloatStore(StoreSDNode* ST) {
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// probably means that we need to integrate dag combiner and legalizer
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// together.
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// We generally can't do this one for long doubles.
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SDValue Tmp1 = ST->getChain();
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SDValue Tmp2 = ST->getBasePtr();
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SDValue Tmp3;
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SDValue Chain = ST->getChain();
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SDValue Ptr = ST->getBasePtr();
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unsigned Alignment = ST->getAlignment();
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bool isVolatile = ST->isVolatile();
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bool isNonTemporal = ST->isNonTemporal();
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@ -652,19 +651,19 @@ SDValue SelectionDAGLegalize::OptimizeFloatStore(StoreSDNode* ST) {
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if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) {
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if (CFP->getValueType(0) == MVT::f32 &&
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TLI.isTypeLegal(MVT::i32)) {
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Tmp3 = DAG.getConstant(CFP->getValueAPF().
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SDValue Con = DAG.getConstant(CFP->getValueAPF().
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bitcastToAPInt().zextOrTrunc(32),
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MVT::i32);
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return DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getPointerInfo(),
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return DAG.getStore(Chain, dl, Con, Ptr, ST->getPointerInfo(),
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isVolatile, isNonTemporal, Alignment);
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}
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if (CFP->getValueType(0) == MVT::f64) {
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// If this target supports 64-bit registers, do a single 64-bit store.
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if (TLI.isTypeLegal(MVT::i64)) {
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Tmp3 = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt().
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SDValue Con = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt().
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zextOrTrunc(64), MVT::i64);
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return DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getPointerInfo(),
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return DAG.getStore(Chain, dl, Con, Ptr, ST->getPointerInfo(),
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isVolatile, isNonTemporal, Alignment);
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}
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@ -677,11 +676,11 @@ SDValue SelectionDAGLegalize::OptimizeFloatStore(StoreSDNode* ST) {
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SDValue Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), MVT::i32);
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if (TLI.isBigEndian()) std::swap(Lo, Hi);
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Lo = DAG.getStore(Tmp1, dl, Lo, Tmp2, ST->getPointerInfo(), isVolatile,
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Lo = DAG.getStore(Chain, dl, Lo, Ptr, ST->getPointerInfo(), isVolatile,
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isNonTemporal, Alignment);
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Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
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Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
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DAG.getIntPtrConstant(4));
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Hi = DAG.getStore(Tmp1, dl, Hi, Tmp2,
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Hi = DAG.getStore(Chain, dl, Hi, Ptr,
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ST->getPointerInfo().getWithOffset(4),
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isVolatile, isNonTemporal, MinAlign(Alignment, 4U));
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@ -694,8 +693,8 @@ SDValue SelectionDAGLegalize::OptimizeFloatStore(StoreSDNode* ST) {
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void SelectionDAGLegalize::LegalizeStoreOps(SDNode *Node) {
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StoreSDNode *ST = cast<StoreSDNode>(Node);
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SDValue Tmp1 = ST->getChain();
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SDValue Tmp2 = ST->getBasePtr();
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SDValue Chain = ST->getChain();
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SDValue Ptr = ST->getBasePtr();
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DebugLoc dl = Node->getDebugLoc();
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unsigned Alignment = ST->getAlignment();
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@ -709,8 +708,8 @@ void SelectionDAGLegalize::LegalizeStoreOps(SDNode *Node) {
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}
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{
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SDValue Tmp3 = ST->getValue();
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EVT VT = Tmp3.getValueType();
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SDValue Value = ST->getValue();
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EVT VT = Value.getValueType();
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switch (TLI.getOperationAction(ISD::STORE, VT)) {
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default: llvm_unreachable("This action is not supported yet!");
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case TargetLowering::Legal:
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@ -724,17 +723,18 @@ void SelectionDAGLegalize::LegalizeStoreOps(SDNode *Node) {
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DAG, TLI, this);
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}
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break;
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case TargetLowering::Custom:
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Tmp1 = TLI.LowerOperation(SDValue(Node, 0), DAG);
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if (Tmp1.getNode())
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ReplaceNode(SDValue(Node, 0), Tmp1);
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break;
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case TargetLowering::Custom: {
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SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG);
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if (Res.getNode())
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ReplaceNode(SDValue(Node, 0), Res);
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return;
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}
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case TargetLowering::Promote: {
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assert(VT.isVector() && "Unknown legal promote case!");
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Tmp3 = DAG.getNode(ISD::BITCAST, dl,
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TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3);
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Value = DAG.getNode(ISD::BITCAST, dl,
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TLI.getTypeToPromoteTo(ISD::STORE, VT), Value);
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SDValue Result =
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DAG.getStore(Tmp1, dl, Tmp3, Tmp2,
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DAG.getStore(Chain, dl, Value, Ptr,
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ST->getPointerInfo(), isVolatile,
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isNonTemporal, Alignment);
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ReplaceNode(SDValue(Node, 0), Result);
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@ -744,7 +744,7 @@ void SelectionDAGLegalize::LegalizeStoreOps(SDNode *Node) {
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return;
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}
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} else {
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SDValue Tmp3 = ST->getValue();
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SDValue Value = ST->getValue();
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EVT StVT = ST->getMemoryVT();
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unsigned StWidth = StVT.getSizeInBits();
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@ -755,9 +755,9 @@ void SelectionDAGLegalize::LegalizeStoreOps(SDNode *Node) {
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// TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1)
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EVT NVT = EVT::getIntegerVT(*DAG.getContext(),
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StVT.getStoreSizeInBits());
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Tmp3 = DAG.getZeroExtendInReg(Tmp3, dl, StVT);
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Value = DAG.getZeroExtendInReg(Value, dl, StVT);
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SDValue Result =
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DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getPointerInfo(),
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DAG.getTruncStore(Chain, dl, Value, Ptr, ST->getPointerInfo(),
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NVT, isVolatile, isNonTemporal, Alignment);
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ReplaceNode(SDValue(Node, 0), Result);
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} else if (StWidth & (StWidth - 1)) {
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@ -777,18 +777,18 @@ void SelectionDAGLegalize::LegalizeStoreOps(SDNode *Node) {
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if (TLI.isLittleEndian()) {
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// TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE@+2:i8 (srl X, 16)
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// Store the bottom RoundWidth bits.
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Lo = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getPointerInfo(),
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Lo = DAG.getTruncStore(Chain, dl, Value, Ptr, ST->getPointerInfo(),
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RoundVT,
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isVolatile, isNonTemporal, Alignment);
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// Store the remaining ExtraWidth bits.
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IncrementSize = RoundWidth / 8;
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Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
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Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
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DAG.getIntPtrConstant(IncrementSize));
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Hi = DAG.getNode(ISD::SRL, dl, Tmp3.getValueType(), Tmp3,
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Hi = DAG.getNode(ISD::SRL, dl, Value.getValueType(), Value,
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DAG.getConstant(RoundWidth,
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TLI.getShiftAmountTy(Tmp3.getValueType())));
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Hi = DAG.getTruncStore(Tmp1, dl, Hi, Tmp2,
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TLI.getShiftAmountTy(Value.getValueType())));
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Hi = DAG.getTruncStore(Chain, dl, Hi, Ptr,
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ST->getPointerInfo().getWithOffset(IncrementSize),
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ExtraVT, isVolatile, isNonTemporal,
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MinAlign(Alignment, IncrementSize));
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@ -796,17 +796,17 @@ void SelectionDAGLegalize::LegalizeStoreOps(SDNode *Node) {
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// Big endian - avoid unaligned stores.
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// TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE@+2:i8 X
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// Store the top RoundWidth bits.
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Hi = DAG.getNode(ISD::SRL, dl, Tmp3.getValueType(), Tmp3,
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Hi = DAG.getNode(ISD::SRL, dl, Value.getValueType(), Value,
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DAG.getConstant(ExtraWidth,
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TLI.getShiftAmountTy(Tmp3.getValueType())));
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Hi = DAG.getTruncStore(Tmp1, dl, Hi, Tmp2, ST->getPointerInfo(),
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TLI.getShiftAmountTy(Value.getValueType())));
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Hi = DAG.getTruncStore(Chain, dl, Hi, Ptr, ST->getPointerInfo(),
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RoundVT, isVolatile, isNonTemporal, Alignment);
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// Store the remaining ExtraWidth bits.
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IncrementSize = RoundWidth / 8;
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Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
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Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
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DAG.getIntPtrConstant(IncrementSize));
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Lo = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2,
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Lo = DAG.getTruncStore(Chain, dl, Value, Ptr,
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ST->getPointerInfo().getWithOffset(IncrementSize),
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ExtraVT, isVolatile, isNonTemporal,
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MinAlign(Alignment, IncrementSize));
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@ -828,20 +828,22 @@ void SelectionDAGLegalize::LegalizeStoreOps(SDNode *Node) {
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ExpandUnalignedStore(cast<StoreSDNode>(Node), DAG, TLI, this);
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}
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break;
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case TargetLowering::Custom:
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Tmp1 = TLI.LowerOperation(SDValue(Node, 0), DAG);
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if (Tmp1.getNode())
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ReplaceNode(SDValue(Node, 0), Tmp1);
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break;
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case TargetLowering::Custom: {
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SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG);
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if (Res.getNode())
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ReplaceNode(SDValue(Node, 0), Res);
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return;
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}
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case TargetLowering::Expand:
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assert(!StVT.isVector() &&
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"Vector Stores are handled in LegalizeVectorOps");
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// TRUNCSTORE:i16 i32 -> STORE i16
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assert(TLI.isTypeLegal(StVT) && "Do not know how to expand this store!");
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Tmp3 = DAG.getNode(ISD::TRUNCATE, dl, StVT, Tmp3);
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assert(TLI.isTypeLegal(StVT) &&
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"Do not know how to expand this store!");
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Value = DAG.getNode(ISD::TRUNCATE, dl, StVT, Value);
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SDValue Result =
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DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getPointerInfo(),
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DAG.getStore(Chain, dl, Value, Ptr, ST->getPointerInfo(),
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isVolatile, isNonTemporal, Alignment);
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ReplaceNode(SDValue(Node, 0), Result);
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break;
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@ -852,15 +854,16 @@ void SelectionDAGLegalize::LegalizeStoreOps(SDNode *Node) {
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void SelectionDAGLegalize::LegalizeLoadOps(SDNode *Node) {
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LoadSDNode *LD = cast<LoadSDNode>(Node);
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SDValue Tmp1 = LD->getChain(); // Legalize the chain.
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SDValue Tmp2 = LD->getBasePtr(); // Legalize the base pointer.
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SDValue Chain = LD->getChain(); // The chain.
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SDValue Ptr = LD->getBasePtr(); // The base pointer.
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SDValue Value; // The value returned by the load op.
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DebugLoc dl = Node->getDebugLoc();
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ISD::LoadExtType ExtType = LD->getExtensionType();
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if (ExtType == ISD::NON_EXTLOAD) {
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EVT VT = Node->getValueType(0);
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SDValue Tmp3 = SDValue(Node, 0);
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SDValue Tmp4 = SDValue(Node, 1);
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SDValue RVal = SDValue(Node, 0);
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SDValue RChain = SDValue(Node, 1);
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switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
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default: llvm_unreachable("This action is not supported yet!");
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@ -869,38 +872,40 @@ void SelectionDAGLegalize::LegalizeLoadOps(SDNode *Node) {
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// expand it.
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if (!TLI.allowsUnalignedMemoryAccesses(LD->getMemoryVT())) {
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Type *Ty = LD->getMemoryVT().getTypeForEVT(*DAG.getContext());
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unsigned ABIAlignment = TLI.getTargetData()->getABITypeAlignment(Ty);
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unsigned ABIAlignment =
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TLI.getTargetData()->getABITypeAlignment(Ty);
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if (LD->getAlignment() < ABIAlignment){
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ExpandUnalignedLoad(cast<LoadSDNode>(Node),
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DAG, TLI, Tmp3, Tmp4);
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DAG, TLI, RVal, RChain);
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}
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}
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break;
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case TargetLowering::Custom:
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Tmp1 = TLI.LowerOperation(Tmp3, DAG);
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if (Tmp1.getNode()) {
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Tmp3 = Tmp1;
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Tmp4 = Tmp1.getValue(1);
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case TargetLowering::Custom: {
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SDValue Res = TLI.LowerOperation(RVal, DAG);
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if (Res.getNode()) {
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RVal = Res;
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RChain = Res.getValue(1);
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}
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break;
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}
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case TargetLowering::Promote: {
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// Only promote a load of vector type to another.
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assert(VT.isVector() && "Cannot promote this load!");
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// Change base type to a different vector type.
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EVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
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Tmp1 = DAG.getLoad(NVT, dl, Tmp1, Tmp2, LD->getPointerInfo(),
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SDValue Res = DAG.getLoad(NVT, dl, Chain, Ptr, LD->getPointerInfo(),
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LD->isVolatile(), LD->isNonTemporal(),
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LD->isInvariant(), LD->getAlignment());
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Tmp3 = DAG.getNode(ISD::BITCAST, dl, VT, Tmp1);
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Tmp4 = Tmp1.getValue(1);
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RVal = DAG.getNode(ISD::BITCAST, dl, VT, Res);
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RChain = Res.getValue(1);
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break;
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}
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}
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if (Tmp4.getNode() != Node) {
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assert(Tmp3.getNode() != Node && "Load must be completely replaced");
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DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), Tmp3);
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DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), Tmp4);
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if (RChain.getNode() != Node) {
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assert(RVal.getNode() != Node && "Load must be completely replaced");
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DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), RVal);
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DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), RChain);
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ReplacedNode(Node);
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}
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return;
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@ -936,7 +941,7 @@ void SelectionDAGLegalize::LegalizeLoadOps(SDNode *Node) {
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SDValue Result =
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DAG.getExtLoad(NewExtType, dl, Node->getValueType(0),
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Tmp1, Tmp2, LD->getPointerInfo(),
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Chain, Ptr, LD->getPointerInfo(),
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NVT, isVolatile, isNonTemporal, Alignment);
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Ch = Result.getValue(1); // The chain.
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@ -952,8 +957,8 @@ void SelectionDAGLegalize::LegalizeLoadOps(SDNode *Node) {
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Result.getValueType(), Result,
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DAG.getValueType(SrcVT));
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Tmp1 = Result;
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Tmp2 = Ch;
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Value = Result;
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Chain = Ch;
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} else if (SrcWidth & (SrcWidth - 1)) {
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// If not loading a power-of-2 number of bits, expand as two loads.
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assert(!SrcVT.isVector() && "Unsupported extload!");
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@ -972,15 +977,15 @@ void SelectionDAGLegalize::LegalizeLoadOps(SDNode *Node) {
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// EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16)
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// Load the bottom RoundWidth bits.
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Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, Node->getValueType(0),
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Tmp1, Tmp2,
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Chain, Ptr,
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LD->getPointerInfo(), RoundVT, isVolatile,
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isNonTemporal, Alignment);
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// Load the remaining ExtraWidth bits.
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IncrementSize = RoundWidth / 8;
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Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
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Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
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DAG.getIntPtrConstant(IncrementSize));
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Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Tmp1, Tmp2,
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Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Chain, Ptr,
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LD->getPointerInfo().getWithOffset(IncrementSize),
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ExtraVT, isVolatile, isNonTemporal,
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MinAlign(Alignment, IncrementSize));
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@ -996,21 +1001,21 @@ void SelectionDAGLegalize::LegalizeLoadOps(SDNode *Node) {
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TLI.getShiftAmountTy(Hi.getValueType())));
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// Join the hi and lo parts.
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Tmp1 = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
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Value = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
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} else {
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// Big endian - avoid unaligned loads.
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// EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8
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// Load the top RoundWidth bits.
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Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Tmp1, Tmp2,
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Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Chain, Ptr,
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LD->getPointerInfo(), RoundVT, isVolatile,
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isNonTemporal, Alignment);
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// Load the remaining ExtraWidth bits.
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IncrementSize = RoundWidth / 8;
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Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
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Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
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DAG.getIntPtrConstant(IncrementSize));
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Lo = DAG.getExtLoad(ISD::ZEXTLOAD,
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dl, Node->getValueType(0), Tmp1, Tmp2,
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dl, Node->getValueType(0), Chain, Ptr,
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LD->getPointerInfo().getWithOffset(IncrementSize),
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ExtraVT, isVolatile, isNonTemporal,
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MinAlign(Alignment, IncrementSize));
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@ -1026,10 +1031,10 @@ void SelectionDAGLegalize::LegalizeLoadOps(SDNode *Node) {
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TLI.getShiftAmountTy(Hi.getValueType())));
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// Join the hi and lo parts.
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Tmp1 = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
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Value = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
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}
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Tmp2 = Ch;
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Chain = Ch;
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} else {
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bool isCustom = false;
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switch (TLI.getLoadExtAction(ExtType, SrcVT)) {
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@ -1037,15 +1042,15 @@ void SelectionDAGLegalize::LegalizeLoadOps(SDNode *Node) {
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case TargetLowering::Custom:
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isCustom = true;
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// FALLTHROUGH
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case TargetLowering::Legal:
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Tmp1 = SDValue(Node, 0);
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Tmp2 = SDValue(Node, 1);
|
||||
case TargetLowering::Legal: {
|
||||
Value = SDValue(Node, 0);
|
||||
Chain = SDValue(Node, 1);
|
||||
|
||||
if (isCustom) {
|
||||
SDValue Tmp3 = TLI.LowerOperation(SDValue(Node, 0), DAG);
|
||||
if (Tmp3.getNode()) {
|
||||
Tmp1 = Tmp3;
|
||||
Tmp2 = Tmp3.getValue(1);
|
||||
SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG);
|
||||
if (Res.getNode()) {
|
||||
Value = Res;
|
||||
Chain = Res.getValue(1);
|
||||
}
|
||||
} else {
|
||||
// If this is an unaligned load and the target doesn't support it,
|
||||
@ -1057,14 +1062,15 @@ void SelectionDAGLegalize::LegalizeLoadOps(SDNode *Node) {
|
||||
TLI.getTargetData()->getABITypeAlignment(Ty);
|
||||
if (LD->getAlignment() < ABIAlignment){
|
||||
ExpandUnalignedLoad(cast<LoadSDNode>(Node),
|
||||
DAG, TLI, Tmp1, Tmp2);
|
||||
DAG, TLI, Value, Chain);
|
||||
}
|
||||
}
|
||||
}
|
||||
break;
|
||||
}
|
||||
case TargetLowering::Expand:
|
||||
if (!TLI.isLoadExtLegal(ISD::EXTLOAD, SrcVT) && TLI.isTypeLegal(SrcVT)) {
|
||||
SDValue Load = DAG.getLoad(SrcVT, dl, Tmp1, Tmp2,
|
||||
SDValue Load = DAG.getLoad(SrcVT, dl, Chain, Ptr,
|
||||
LD->getPointerInfo(),
|
||||
LD->isVolatile(), LD->isNonTemporal(),
|
||||
LD->isInvariant(), LD->getAlignment());
|
||||
@ -1078,8 +1084,8 @@ void SelectionDAGLegalize::LegalizeLoadOps(SDNode *Node) {
|
||||
case ISD::ZEXTLOAD: ExtendOp = ISD::ZERO_EXTEND; break;
|
||||
default: llvm_unreachable("Unexpected extend load type!");
|
||||
}
|
||||
Tmp1 = DAG.getNode(ExtendOp, dl, Node->getValueType(0), Load);
|
||||
Tmp2 = Load.getValue(1);
|
||||
Value = DAG.getNode(ExtendOp, dl, Node->getValueType(0), Load);
|
||||
Chain = Load.getValue(1);
|
||||
break;
|
||||
}
|
||||
|
||||
@ -1095,7 +1101,7 @@ void SelectionDAGLegalize::LegalizeLoadOps(SDNode *Node) {
|
||||
// Turn the unsupported load into an EXTLOAD followed by an explicit
|
||||
// zero/sign extend inreg.
|
||||
SDValue Result = DAG.getExtLoad(ISD::EXTLOAD, dl, Node->getValueType(0),
|
||||
Tmp1, Tmp2, LD->getPointerInfo(), SrcVT,
|
||||
Chain, Ptr, LD->getPointerInfo(), SrcVT,
|
||||
LD->isVolatile(), LD->isNonTemporal(),
|
||||
LD->getAlignment());
|
||||
SDValue ValRes;
|
||||
@ -1105,18 +1111,18 @@ void SelectionDAGLegalize::LegalizeLoadOps(SDNode *Node) {
|
||||
Result, DAG.getValueType(SrcVT));
|
||||
else
|
||||
ValRes = DAG.getZeroExtendInReg(Result, dl, SrcVT.getScalarType());
|
||||
Tmp1 = ValRes;
|
||||
Tmp2 = Result.getValue(1);
|
||||
Value = ValRes;
|
||||
Chain = Result.getValue(1);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
// Since loads produce two values, make sure to remember that we legalized
|
||||
// both of them.
|
||||
if (Tmp2.getNode() != Node) {
|
||||
assert(Tmp1.getNode() != Node && "Load must be completely replaced");
|
||||
DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), Tmp1);
|
||||
DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), Tmp2);
|
||||
if (Chain.getNode() != Node) {
|
||||
assert(Value.getNode() != Node && "Load must be completely replaced");
|
||||
DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), Value);
|
||||
DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), Chain);
|
||||
ReplacedNode(Node);
|
||||
}
|
||||
}
|
||||
@ -1139,8 +1145,6 @@ void SelectionDAGLegalize::LegalizeOp(SDNode *Node) {
|
||||
Node->getOperand(i).getOpcode() == ISD::TargetConstant) &&
|
||||
"Unexpected illegal type!");
|
||||
|
||||
SDValue Tmp1, Tmp2, Tmp3, Tmp4;
|
||||
|
||||
// Figure out the correct action; the way to query this varies by opcode
|
||||
TargetLowering::LegalizeAction Action = TargetLowering::Legal;
|
||||
bool SimpleFinishLegalizing = true;
|
||||
@ -1294,19 +1298,19 @@ void SelectionDAGLegalize::LegalizeOp(SDNode *Node) {
|
||||
switch (Action) {
|
||||
case TargetLowering::Legal:
|
||||
return;
|
||||
case TargetLowering::Custom:
|
||||
case TargetLowering::Custom: {
|
||||
// FIXME: The handling for custom lowering with multiple results is
|
||||
// a complete mess.
|
||||
Tmp1 = TLI.LowerOperation(SDValue(Node, 0), DAG);
|
||||
if (Tmp1.getNode()) {
|
||||
SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG);
|
||||
if (Res.getNode()) {
|
||||
SmallVector<SDValue, 8> ResultVals;
|
||||
for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) {
|
||||
if (e == 1)
|
||||
ResultVals.push_back(Tmp1);
|
||||
ResultVals.push_back(Res);
|
||||
else
|
||||
ResultVals.push_back(Tmp1.getValue(i));
|
||||
ResultVals.push_back(Res.getValue(i));
|
||||
}
|
||||
if (Tmp1.getNode() != Node || Tmp1.getResNo() != 0) {
|
||||
if (Res.getNode() != Node || Res.getResNo() != 0) {
|
||||
DAG.ReplaceAllUsesWith(Node, ResultVals.data());
|
||||
for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
|
||||
DAG.TransferDbgValues(SDValue(Node, i), ResultVals[i]);
|
||||
@ -1314,7 +1318,7 @@ void SelectionDAGLegalize::LegalizeOp(SDNode *Node) {
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
||||
}
|
||||
// FALL THROUGH
|
||||
case TargetLowering::Expand:
|
||||
ExpandNode(Node);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user