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Make sure we're only storing a single bit here.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118126 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Eric Christopher 2010-11-02 23:59:09 +00:00
parent 491561dcac
commit 4c914125c4
1 changed files with 9 additions and 2 deletions
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11
lib/Target/ARM/ARMFastISel.cpp
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@ -811,7 +811,15 @@ bool ARMFastISel::ARMEmitStore(EVT VT, unsigned SrcReg,
bool needReg0Op = false;
switch (VT.getSimpleVT().SimpleTy) {
default: return false;
case MVT::i1:
case MVT::i1: {
unsigned Res = createResultReg(isThumb ? ARM::tGPRRegisterClass :
ARM::GPRRegisterClass);
unsigned Opc = isThumb ? ARM::t2ANDri : ARM::ANDri;
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
TII.get(Opc), Res)
.addReg(SrcReg).addImm(1));
SrcReg = Res;
} // Fallthrough here.
case MVT::i8:
StrOpc = isThumb ? ARM::t2STRBi12 : ARM::STRBi12;
break;
@ -841,7 +849,6 @@ bool ARMFastISel::ARMEmitStore(EVT VT, unsigned SrcReg,
if (isFloat)
Offset /= 4;
// FIXME: The 'needReg0Op' bit goes away once STRH is converted to
// not use the mega-addrmode stuff.
if (!needReg0Op)