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Fix FP_TO_UINT->i32 on ppc32 -mcpu=g5. This was
using Promote which won't work because i64 isn't a legal type. It's easy enough to use Custom, but then we have the problem that when the type legalizer is promoting FP_TO_UINT->i16, it has no way of telling it should prefer FP_TO_SINT->i32 to FP_TO_UINT->i32. I have uncomfortably hacked this by making the type legalizer choose FP_TO_SINT when both are Custom. This fixes several regressions in the testsuite. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72891 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -356,13 +356,12 @@ SDValue DAGTypeLegalizer::PromoteIntRes_FP_TO_XINT(SDNode *N) {
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unsigned NewOpc = N->getOpcode();
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DebugLoc dl = N->getDebugLoc();
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// If we're promoting a UINT to a larger size, check to see if the new node
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// will be legal. If it isn't, check to see if FP_TO_SINT is legal, since
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// we can use that instead. This allows us to generate better code for
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// FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not
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// legal, such as PowerPC.
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// If we're promoting a UINT to a larger size and the larger FP_TO_UINT is
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// not Legal, check to see if we can use FP_TO_SINT instead. (If both UINT
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// and SINT conversions are Custom, there is no way to tell which is preferable.
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// We choose SINT because that's the right thing on PPC.)
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if (N->getOpcode() == ISD::FP_TO_UINT &&
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!TLI.isOperationLegalOrCustom(ISD::FP_TO_UINT, NVT) &&
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!TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
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TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NVT))
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NewOpc = ISD::FP_TO_SINT;
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@ -227,15 +227,14 @@ PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM)
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setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
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setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
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setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
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setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
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// This is just the low 32 bits of a (signed) fp->i64 conversion.
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// We cannot do this with Promote because i64 is not a legal type.
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setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
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// FIXME: disable this lowered code. This generates 64-bit register values,
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// and we don't model the fact that the top part is clobbered by calls. We
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// need to flag these together so that the value isn't live across a call.
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//setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
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// To take advantage of the above i64 FP_TO_SINT, promote i32 FP_TO_UINT
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setOperationAction(ISD::FP_TO_UINT, MVT::i32, Promote);
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} else {
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// PowerPC does not have FP_TO_UINT on 32-bit implementations.
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setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
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@ -2858,7 +2857,7 @@ SDValue PPCTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) {
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}
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// FIXME: Split this code up when LegalizeDAGTypes lands.
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SDValue PPCTargetLowering::LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG,
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SDValue PPCTargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG,
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DebugLoc dl) {
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assert(Op.getOperand(0).getValueType().isFloatingPoint());
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SDValue Src = Op.getOperand(0);
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@ -2867,9 +2866,11 @@ SDValue PPCTargetLowering::LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG,
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SDValue Tmp;
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switch (Op.getValueType().getSimpleVT()) {
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default: assert(0 && "Unhandled FP_TO_SINT type in custom expander!");
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default: assert(0 && "Unhandled FP_TO_INT type in custom expander!");
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case MVT::i32:
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Tmp = DAG.getNode(PPCISD::FCTIWZ, dl, MVT::f64, Src);
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Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIWZ :
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PPCISD::FCTIDZ,
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dl, MVT::f64, Src);
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break;
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case MVT::i64:
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Tmp = DAG.getNode(PPCISD::FCTIDZ, dl, MVT::f64, Src);
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@ -3740,7 +3741,8 @@ SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
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return LowerDYNAMIC_STACKALLOC(Op, DAG, PPCSubTarget);
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case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
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case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG,
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case ISD::FP_TO_UINT:
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case ISD::FP_TO_SINT: return LowerFP_TO_INT(Op, DAG,
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Op.getDebugLoc());
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case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
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case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
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@ -3834,7 +3836,7 @@ void PPCTargetLowering::ReplaceNodeResults(SDNode *N,
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return;
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}
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case ISD::FP_TO_SINT:
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Results.push_back(LowerFP_TO_SINT(SDValue(N, 0), DAG, dl));
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Results.push_back(LowerFP_TO_INT(SDValue(N, 0), DAG, dl));
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return;
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}
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}
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@ -377,7 +377,7 @@ namespace llvm {
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SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG,
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const PPCSubtarget &Subtarget);
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SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG);
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SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG, DebugLoc dl);
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SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG, DebugLoc dl);
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SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG);
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SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG);
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SDValue LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG);
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