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https://github.com/c64scene-ar/llvm-6502.git
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* Move information about Implicit Defs/Uses into X86InstrInfo.def.
* Expose information about implicit defs/uses of register through the MachineInstrInfo.h file. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4877 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner
parent
6af204077c
commit
4ce42a776a
@ -52,7 +52,7 @@ namespace X86 {
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// This defines a large number of symbolic names for X86 instruction opcodes.
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enum Opcode {
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#define I(ENUM, NAME, BASEOPCODE, FLAGS, TSFLAGS) ENUM,
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#define I(ENUM, NAME, BASEOPCODE, FLAGS, TSFLAGS, IMPDEFS, IMPUSES) ENUM,
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#include "X86InstrInfo.def"
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};
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}
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@ -1,87 +0,0 @@
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//===-- X86Implicit.cpp - All the implicit uses and defs for X86 ops ------===//
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//
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// This defines a class which maps X86 opcodes to the registers that they
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// implicitly modify or use.
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//
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//===----------------------------------------------------------------------===//
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#include "X86Implicit.h"
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#include <map>
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#include <vector>
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X86Implicit::X86Implicit ()
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{
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implicitUses[X86::CBW].push_back (X86::AL);
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implicitDefs[X86::CBW].push_back (X86::AX);
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implicitUses[X86::CDQ].push_back (X86::EAX);
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implicitDefs[X86::CDQ].push_back (X86::EDX);
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implicitUses[X86::CWD].push_back (X86::AX);
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implicitDefs[X86::CWD].push_back (X86::DX);
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implicitUses[X86::DIVrr16].push_back (X86::DX);
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implicitUses[X86::DIVrr16].push_back (X86::AX);
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implicitDefs[X86::DIVrr16].push_back (X86::DX);
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implicitDefs[X86::DIVrr16].push_back (X86::AX);
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implicitUses[X86::DIVrr32].push_back (X86::EDX);
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implicitUses[X86::DIVrr32].push_back (X86::EAX);
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implicitDefs[X86::DIVrr32].push_back (X86::EDX);
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implicitDefs[X86::DIVrr32].push_back (X86::EAX);
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implicitUses[X86::DIVrr8].push_back (X86::AX);
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implicitDefs[X86::DIVrr8].push_back (X86::AL);
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implicitDefs[X86::DIVrr8].push_back (X86::AH);
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implicitDefs[X86::FNSTSWr8].push_back (X86::AX);
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implicitUses[X86::IDIVrr16].push_back (X86::DX);
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implicitUses[X86::IDIVrr16].push_back (X86::AX);
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implicitDefs[X86::IDIVrr16].push_back (X86::DX);
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implicitDefs[X86::IDIVrr16].push_back (X86::AX);
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implicitUses[X86::IDIVrr32].push_back (X86::EDX);
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implicitUses[X86::IDIVrr32].push_back (X86::EAX);
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implicitDefs[X86::IDIVrr32].push_back (X86::EDX);
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implicitDefs[X86::IDIVrr32].push_back (X86::EAX);
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implicitUses[X86::IDIVrr8].push_back (X86::AX);
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implicitDefs[X86::IDIVrr8].push_back (X86::AL);
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implicitDefs[X86::IDIVrr8].push_back (X86::AH);
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implicitUses[X86::LEAVE].push_back (X86::EBP);
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implicitDefs[X86::LEAVE].push_back (X86::EBP);
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implicitUses[X86::MULrr16].push_back (X86::AX);
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implicitDefs[X86::MULrr16].push_back (X86::DX);
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implicitDefs[X86::MULrr16].push_back (X86::AX);
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implicitUses[X86::MULrr32].push_back (X86::EAX);
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implicitDefs[X86::MULrr32].push_back (X86::EDX);
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implicitDefs[X86::MULrr32].push_back (X86::EAX);
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implicitUses[X86::MULrr8].push_back (X86::AL);
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implicitDefs[X86::MULrr8].push_back (X86::AX);
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implicitUses[X86::SAHF].push_back (X86::AH);
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implicitUses[X86::SARrr16].push_back (X86::CL);
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implicitUses[X86::SARrr32].push_back (X86::CL);
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implicitUses[X86::SARrr8].push_back (X86::CL);
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implicitUses[X86::SHLrr16].push_back (X86::CL);
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implicitUses[X86::SHLrr32].push_back (X86::CL);
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implicitUses[X86::SHLrr8].push_back (X86::CL);
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implicitUses[X86::SHRrr16].push_back (X86::CL);
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implicitUses[X86::SHRrr32].push_back (X86::CL);
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implicitUses[X86::SHRrr8].push_back (X86::CL);
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}
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@ -1,18 +0,0 @@
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//===-- X86Implicit.h - All the implicit uses and defs for X86 ops --------===//
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//
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// This defines a class which maps X86 opcodes to the registers that they
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// implicitly modify or use.
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//
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//===----------------------------------------------------------------------===//
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#include "X86.h"
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#include <map>
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#include <vector>
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class X86Implicit {
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public:
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typedef std::map <X86::Opcode, std::vector <X86::Register> > ImplicitMap;
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ImplicitMap implicitUses;
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ImplicitMap implicitDefs;
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X86Implicit ();
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};
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@ -5,18 +5,24 @@
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//===----------------------------------------------------------------------===//
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#include "X86InstrInfo.h"
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#include "X86.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include <iostream>
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#define I(ENUM, NAME, BASEOPCODE, FLAGS, TSFLAGS, IMPDEFS, IMPUSES)
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#define IMPREGSLIST(NAME, ...) \
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static const unsigned NAME[] = { __VA_ARGS__ };
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#include "X86InstrInfo.def"
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// X86Insts - Turn the InstrInfo.def file into a bunch of instruction
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// descriptors
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//
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static const MachineInstrDescriptor X86Insts[] = {
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#define I(ENUM, NAME, BASEOPCODE, FLAGS, TSFLAGS) \
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#define I(ENUM, NAME, BASEOPCODE, FLAGS, TSFLAGS, IMPDEFS, IMPUSES) \
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{ NAME, \
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-1, /* Always vararg */ \
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((TSFLAGS) & X86II::Void) ? -1 : 0, /* Result is in 0 */ \
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0, false, 0, 0, TSFLAGS, FLAGS, TSFLAGS },
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0, false, 0, 0, TSFLAGS, FLAGS, TSFLAGS, IMPDEFS, IMPUSES },
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#include "X86InstrInfo.def"
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};
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@ -26,7 +32,7 @@ X86InstrInfo::X86InstrInfo()
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static unsigned char BaseOpcodes[] = {
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#define I(ENUM, NAME, BASEOPCODE, FLAGS, TSFLAGS) BASEOPCODE,
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#define I(ENUM, NAME, BASEOPCODE, FLAGS, TSFLAGS, IMPDEFS, IMPUSES) BASEOPCODE,
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#include "X86InstrInfo.def"
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};
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@ -17,6 +17,27 @@
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#errror "Must define I macro before including X86/X86InstructionInfo.def!"
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#endif
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// Macro to handle the implicit register uses lists...
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#ifndef IMPREGSLIST
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#define IMPREGSLIST(NAME, ...)
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#endif
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// Implicit register usage info: O_ is for one register, T_ is for two registers
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IMPREGSLIST(NoImpRegs, 0)
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IMPREGSLIST(O_AL , X86::AL , 0)
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IMPREGSLIST(O_AH , X86::AH , 0)
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IMPREGSLIST(O_CL , X86::CL , 0)
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IMPREGSLIST(O_AX , X86::AX , 0)
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IMPREGSLIST(O_DX , X86::DX , 0)
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IMPREGSLIST(O_EAX , X86::EAX, 0)
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IMPREGSLIST(O_EDX , X86::EDX, 0)
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IMPREGSLIST(O_EBP , X86::EBP, 0)
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IMPREGSLIST(T_AXDX , X86::AX , X86::DX , 0)
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IMPREGSLIST(T_EAXEDX , X86::EAX, X86::EDX, 0)
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#undef IMPREGSLIST
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// Arguments to be passed into the I macro
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// #1: Enum name - This ends up being the opcode symbol in the X86 namespace
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// #2: Opcode name, as used by the gnu assembler
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@ -26,137 +47,139 @@
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// #5: Target Specific Flags - Another bitfield containing X86 specific flags
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// that we are interested in for each instruction. These should be flags
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// defined in X86InstrInfo.h in the X86II namespace.
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// #6: Name of the implicit register uses list
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// #7: Name of the implicit register definitions list
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//
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// The first instruction must always be the PHI instruction:
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I(PHI , "phi", 0, 0, 0)
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I(PHI , "phi", 0, 0, 0, NoImpRegs, NoImpRegs)
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// The second instruction must always be the noop instruction:
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I(NOOP , "nop", 0x90, 0, X86II::RawFrm | X86II::Void) // nop
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I(NOOP , "nop", 0x90, 0, X86II::RawFrm | X86II::Void, NoImpRegs, NoImpRegs) // nop
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// Flow control instructions
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I(RET , "ret", 0xCB, M_RET_FLAG, X86II::RawFrm | X86II::Void) // ret
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I(JMP , "jmp", 0xE9, M_BRANCH_FLAG, X86II::RawFrm | X86II::Void) // jmp foo
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I(JNE , "jne", 0x85, M_BRANCH_FLAG, X86II::RawFrm | X86II::TB | X86II::Void)
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I(JE , "je", 0x84, M_BRANCH_FLAG, X86II::RawFrm | X86II::TB | X86II::Void)
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I(CALLpcrel32 , "call", 0xE8, M_BRANCH_FLAG, X86II::Void)
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I(RET , "ret", 0xCB, M_RET_FLAG, X86II::RawFrm | X86II::Void, NoImpRegs, NoImpRegs) // ret
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I(JMP , "jmp", 0xE9, M_BRANCH_FLAG, X86II::RawFrm | X86II::Void, NoImpRegs, NoImpRegs) // jmp foo
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I(JNE , "jne", 0x85, M_BRANCH_FLAG, X86II::RawFrm | X86II::TB | X86II::Void, NoImpRegs, NoImpRegs)
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I(JE , "je", 0x84, M_BRANCH_FLAG, X86II::RawFrm | X86II::TB | X86II::Void, NoImpRegs, NoImpRegs)
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I(CALLpcrel32 , "call", 0xE8, M_BRANCH_FLAG, X86II::Void, NoImpRegs, NoImpRegs)
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// Misc instructions
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I(LEAVE , "leave", 0xC9, 0, X86II::RawFrm) // leave
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I(LEAVE , "leave", 0xC9, 0, X86II::RawFrm, O_EBP, O_EBP) // leave
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// Move instructions
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I(MOVrr8 , "movb", 0x88, 0, X86II::MRMDestReg) // R8 = R8
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I(MOVrr16 , "movw", 0x89, 0, X86II::MRMDestReg | X86II::OpSize) // R16 = R16
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I(MOVrr32 , "movl", 0x89, 0, X86II::MRMDestReg) // R32 = R32
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I(MOVir8 , "movb", 0xB0, 0, X86II::AddRegFrm) // R8 = imm8
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I(MOVir16 , "movw", 0xB8, 0, X86II::AddRegFrm | X86II::OpSize) // R16 = imm16
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I(MOVir32 , "movl", 0xB8, 0, X86II::AddRegFrm) // R32 = imm32
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I(MOVmr8 , "movb", 0x8A, 0, X86II::MRMSrcMem) // R8 = [mem] 8A/r
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I(MOVmr16 , "movw", 0x8B, 0, X86II::MRMSrcMem | X86II::OpSize) // R16 = [mem] 8B/r
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I(MOVmr32 , "movl", 0x8B, 0, X86II::MRMSrcMem) // R32 = [mem] 8B/r
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I(MOVrm8 , "movb", 0x88, 0, X86II::MRMDestMem | X86II::Void) // [mem] = R8 88/r
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I(MOVrm16 , "movw", 0x89, 0, X86II::MRMDestMem | X86II::Void | // [mem] = R16 89/r
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X86II::OpSize)
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I(MOVrm32 , "movl", 0x89, 0, X86II::MRMDestMem | X86II::Void) // [mem] = R32 89/r
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I(MOVrr8 , "movb", 0x88, 0, X86II::MRMDestReg, NoImpRegs, NoImpRegs) // R8 = R8
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I(MOVrr16 , "movw", 0x89, 0, X86II::MRMDestReg | X86II::OpSize, NoImpRegs, NoImpRegs) // R16 = R16
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I(MOVrr32 , "movl", 0x89, 0, X86II::MRMDestReg, NoImpRegs, NoImpRegs) // R32 = R32
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I(MOVir8 , "movb", 0xB0, 0, X86II::AddRegFrm, NoImpRegs, NoImpRegs) // R8 = imm8
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I(MOVir16 , "movw", 0xB8, 0, X86II::AddRegFrm | X86II::OpSize, NoImpRegs, NoImpRegs) // R16 = imm16
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I(MOVir32 , "movl", 0xB8, 0, X86II::AddRegFrm, NoImpRegs, NoImpRegs) // R32 = imm32
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I(MOVmr8 , "movb", 0x8A, 0, X86II::MRMSrcMem, NoImpRegs, NoImpRegs) // R8 = [mem]
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I(MOVmr16 , "movw", 0x8B, 0, X86II::MRMSrcMem | X86II::OpSize, NoImpRegs, NoImpRegs) // R16 = [mem]
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I(MOVmr32 , "movl", 0x8B, 0, X86II::MRMSrcMem, NoImpRegs, NoImpRegs) // R32 = [mem]
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I(MOVrm8 , "movb", 0x88, 0, X86II::MRMDestMem | X86II::Void, NoImpRegs, NoImpRegs) // [mem] = R8
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I(MOVrm16 , "movw", 0x89, 0, X86II::MRMDestMem | X86II::Void | // [mem] = R16
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X86II::OpSize, NoImpRegs, NoImpRegs)
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I(MOVrm32 , "movl", 0x89, 0, X86II::MRMDestMem | X86II::Void, NoImpRegs, NoImpRegs) // [mem] = R32
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I(PUSHr32 , "pushl", 0x50, 0, X86II::AddRegFrm | X86II::Void)
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I(PUSHr32 , "pushl", 0x50, 0, X86II::AddRegFrm | X86II::Void, NoImpRegs, NoImpRegs)
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// Arithmetic instructions
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I(ADDrr8 , "addb", 0x00, 0, X86II::MRMDestReg) // R8 += R8
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I(ADDrr16 , "addw", 0x01, 0, X86II::MRMDestReg | X86II::OpSize) // R16 += R16
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I(ADDrr32 , "addl", 0x01, 0, X86II::MRMDestReg) // R32 += R32
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I(SUBrr8 , "subb", 0x2A, 0, X86II::MRMDestReg) // R8 -= R8
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I(SUBrr16 , "subw", 0x2B, 0, X86II::MRMDestReg | X86II::OpSize) // R16 -= R16
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I(SUBrr32 , "subl", 0x2B, 0, X86II::MRMDestReg) // R32 -= R32
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I(MULrr8 , "mulb", 0xF6, 0, X86II::MRMS4r | X86II::Void) // AX = AL*R8
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I(MULrr16 , "mulw", 0xF7, 0, X86II::MRMS4r | X86II::Void | // DX:AX= AX*R16
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X86II::OpSize)
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I(MULrr32 , "mull", 0xF7, 0, X86II::MRMS4r | X86II::Void) // ED:EA= EA*R32
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I(ADDrr8 , "addb", 0x00, 0, X86II::MRMDestReg, NoImpRegs, NoImpRegs) // R8 += R8
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I(ADDrr16 , "addw", 0x01, 0, X86II::MRMDestReg | X86II::OpSize, NoImpRegs, NoImpRegs) // R16 += R16
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I(ADDrr32 , "addl", 0x01, 0, X86II::MRMDestReg, NoImpRegs, NoImpRegs) // R32 += R32
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I(SUBrr8 , "subb", 0x2A, 0, X86II::MRMDestReg, NoImpRegs, NoImpRegs) // R8 -= R8
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I(SUBrr16 , "subw", 0x2B, 0, X86II::MRMDestReg | X86II::OpSize, NoImpRegs, NoImpRegs) // R16 -= R16
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I(SUBrr32 , "subl", 0x2B, 0, X86II::MRMDestReg, NoImpRegs, NoImpRegs) // R32 -= R32
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I(MULrr8 , "mulb", 0xF6, 0, X86II::MRMS4r | X86II::Void, O_AL, O_AX) // AX = AL*R8
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I(MULrr16 , "mulw", 0xF7, 0, X86II::MRMS4r | X86II::Void | // DX:AX= AX*R16
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X86II::OpSize, O_AX, T_AXDX)
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I(MULrr32 , "mull", 0xF7, 0, X86II::MRMS4r | X86II::Void, O_EAX, T_EAXEDX) // ED:EA= EA*R32
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// unsigned division/remainder
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I(DIVrr8 , "divb", 0xF6, 0, X86II::MRMS6r | X86II::Void) // AX/r8= AL&AH
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I(DIVrr16 , "divw", 0xF7, 0, X86II::MRMS6r | X86II::Void | // DA/r16=AX&DX
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X86II::OpSize)
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I(DIVrr32 , "divl", 0xF7, 0, X86II::MRMS6r | X86II::Void) // DA/r32=EAX&DX
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I(DIVrr8 , "divb", 0xF6, 0, X86II::MRMS6r | X86II::Void, O_AX, O_AX) // AX/r8= AL&AH
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I(DIVrr16 , "divw", 0xF7, 0, X86II::MRMS6r | X86II::Void | // EDXEAX/r16=AX&DX
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X86II::OpSize, T_AXDX, T_AXDX)
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I(DIVrr32 , "divl", 0xF7, 0, X86II::MRMS6r | X86II::Void, T_EAXEDX, T_EAXEDX) // EDXEAX/r32=EAX&EDX
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// signed division/remainder
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I(IDIVrr8 , "idivb", 0xF6, 0, X86II::MRMS7r | X86II::Void) // AX/r8= AL&AH
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I(IDIVrr16 , "idivw", 0xF7, 0, X86II::MRMS7r | X86II::Void | // DA/r16=AX&DX
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X86II::OpSize)
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I(IDIVrr32 , "idivl", 0xF7, 0, X86II::MRMS7r | X86II::Void) // DA/r32=EAX&DX
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I(IDIVrr8 , "idivb", 0xF6, 0, X86II::MRMS7r | X86II::Void, O_AX, O_AX) // AX/r8= AL&AH
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I(IDIVrr16 , "idivw", 0xF7, 0, X86II::MRMS7r | X86II::Void | // DA/r16=AX&DX
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X86II::OpSize, T_AXDX, T_AXDX)
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I(IDIVrr32 , "idivl", 0xF7, 0, X86II::MRMS7r | X86II::Void, T_EAXEDX, T_EAXEDX) // DA/r32=EAX&DX
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// Logical operators
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I(ANDrr8 , "andb", 0x20, 0, X86II::MRMDestReg) // R8 &= R8
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I(ANDrr16 , "andw", 0x21, 0, X86II::MRMDestReg | X86II::OpSize) // R16 &= R16
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I(ANDrr32 , "andl", 0x21, 0, X86II::MRMDestReg) // R32 &= R32
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I(ORrr8 , "orb", 0x08, 0, X86II::MRMDestReg) // R8 |= R8
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I(ORrr16 , "orw", 0x09, 0, X86II::MRMDestReg | X86II::OpSize) // R16 |= R16
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I(ORrr32 , "orl", 0x09, 0, X86II::MRMDestReg) // R32 |= R32
|
||||
I(XORrr8 , "xorb", 0x30, 0, X86II::MRMDestReg) // R8 ^= R8
|
||||
I(XORrr16 , "xorw", 0x31, 0, X86II::MRMDestReg | X86II::OpSize) // R16 ^= R16
|
||||
I(XORrr32 , "xorl", 0x31, 0, X86II::MRMDestReg) // R32 ^= R32
|
||||
I(ANDrr8 , "andb", 0x20, 0, X86II::MRMDestReg, NoImpRegs, NoImpRegs) // R8 &= R8
|
||||
I(ANDrr16 , "andw", 0x21, 0, X86II::MRMDestReg | X86II::OpSize, NoImpRegs, NoImpRegs) // R16 &= R16
|
||||
I(ANDrr32 , "andl", 0x21, 0, X86II::MRMDestReg, NoImpRegs, NoImpRegs) // R32 &= R32
|
||||
I(ORrr8 , "orb", 0x08, 0, X86II::MRMDestReg, NoImpRegs, NoImpRegs) // R8 |= R8
|
||||
I(ORrr16 , "orw", 0x09, 0, X86II::MRMDestReg | X86II::OpSize, NoImpRegs, NoImpRegs) // R16 |= R16
|
||||
I(ORrr32 , "orl", 0x09, 0, X86II::MRMDestReg, NoImpRegs, NoImpRegs) // R32 |= R32
|
||||
I(XORrr8 , "xorb", 0x30, 0, X86II::MRMDestReg, NoImpRegs, NoImpRegs) // R8 ^= R8
|
||||
I(XORrr16 , "xorw", 0x31, 0, X86II::MRMDestReg | X86II::OpSize, NoImpRegs, NoImpRegs) // R16 ^= R16
|
||||
I(XORrr32 , "xorl", 0x31, 0, X86II::MRMDestReg, NoImpRegs, NoImpRegs) // R32 ^= R32
|
||||
|
||||
// Shift instructions
|
||||
I(SHLrr8 , "shlb", 0xD2, 0, X86II::MRMS4r) // R8 <<= cl D2/4
|
||||
I(SHLrr16 , "shlw", 0xD3, 0, X86II::MRMS4r | X86II::OpSize) // R16 <<= cl D3/4
|
||||
I(SHLrr32 , "shll", 0xD3, 0, X86II::MRMS4r) // R32 <<= cl D3/4
|
||||
I(SHLir8 , "shlb", 0xC0, 0, X86II::MRMS4r) // R8 <<= imm8 C0/4 ib
|
||||
I(SHLir16 , "shlw", 0xC1, 0, X86II::MRMS4r | X86II::OpSize) // R16 <<= imm8 C1/4 ib
|
||||
I(SHLir32 , "shll", 0xC1, 0, X86II::MRMS4r) // R32 <<= imm8 C1/4 ib
|
||||
I(SHRrr8 , "shrb", 0xD2, 0, X86II::MRMS5r) // R8 >>>= cl D2/5
|
||||
I(SHRrr16 , "shrw", 0xD3, 0, X86II::MRMS5r | X86II::OpSize) // R16 >>>= cl D3/5
|
||||
I(SHRrr32 , "shrl", 0xD3, 0, X86II::MRMS5r) // R32 >>>= cl D3/5
|
||||
I(SHRir8 , "shrb", 0xC0, 0, X86II::MRMS5r) // R8 >>>= imm8 C0/5 ib
|
||||
I(SHRir16 , "shrw", 0xC1, 0, X86II::MRMS5r | X86II::OpSize) // R16 >>>= imm8 C1/5 ib
|
||||
I(SHRir32 , "shrl", 0xC1, 0, X86II::MRMS5r) // R32 >>>= imm8 C1/5 ib
|
||||
I(SARrr8 , "sarb", 0xD2, 0, X86II::MRMS7r) // R8 >>= cl D2/7
|
||||
I(SARrr16 , "sarw", 0xD3, 0, X86II::MRMS7r | X86II::OpSize) // R16 >>= cl D3/7
|
||||
I(SARrr32 , "sarl", 0xD3, 0, X86II::MRMS7r) // R32 >>= cl D3/7
|
||||
I(SARir8 , "sarb", 0xC0, 0, X86II::MRMS7r) // R8 >>= imm8 C0/7 ib
|
||||
I(SARir16 , "sarw", 0xC1, 0, X86II::MRMS7r | X86II::OpSize) // R16 >>= imm8 C1/7 ib
|
||||
I(SARir32 , "sarl", 0xC1, 0, X86II::MRMS7r) // R32 >>= imm8 C1/7 ib
|
||||
I(SHLrr8 , "shlb", 0xD2, 0, X86II::MRMS4r, O_CL, NoImpRegs) // R8 <<= cl D2/4
|
||||
I(SHLrr16 , "shlw", 0xD3, 0, X86II::MRMS4r | X86II::OpSize, O_CL, NoImpRegs) // R16 <<= cl D3/4
|
||||
I(SHLrr32 , "shll", 0xD3, 0, X86II::MRMS4r, O_CL, NoImpRegs) // R32 <<= cl D3/4
|
||||
I(SHLir8 , "shlb", 0xC0, 0, X86II::MRMS4r, NoImpRegs, NoImpRegs) // R8 <<= imm8 C0/4 ib
|
||||
I(SHLir16 , "shlw", 0xC1, 0, X86II::MRMS4r | X86II::OpSize, NoImpRegs, NoImpRegs) // R16 <<= imm8 C1/4 ib
|
||||
I(SHLir32 , "shll", 0xC1, 0, X86II::MRMS4r, NoImpRegs, NoImpRegs) // R32 <<= imm8 C1/4 ib
|
||||
I(SHRrr8 , "shrb", 0xD2, 0, X86II::MRMS5r, O_CL, NoImpRegs) // R8 >>>= cl D2/5
|
||||
I(SHRrr16 , "shrw", 0xD3, 0, X86II::MRMS5r | X86II::OpSize, O_CL, NoImpRegs) // R16 >>>= cl D3/5
|
||||
I(SHRrr32 , "shrl", 0xD3, 0, X86II::MRMS5r, O_CL, NoImpRegs) // R32 >>>= cl D3/5
|
||||
I(SHRir8 , "shrb", 0xC0, 0, X86II::MRMS5r, NoImpRegs, NoImpRegs) // R8 >>>= imm8 C0/5 ib
|
||||
I(SHRir16 , "shrw", 0xC1, 0, X86II::MRMS5r | X86II::OpSize, NoImpRegs, NoImpRegs) // R16 >>>= imm8 C1/5 ib
|
||||
I(SHRir32 , "shrl", 0xC1, 0, X86II::MRMS5r, NoImpRegs, NoImpRegs) // R32 >>>= imm8 C1/5 ib
|
||||
I(SARrr8 , "sarb", 0xD2, 0, X86II::MRMS7r, O_CL, NoImpRegs) // R8 >>= cl D2/7
|
||||
I(SARrr16 , "sarw", 0xD3, 0, X86II::MRMS7r | X86II::OpSize, O_CL, NoImpRegs) // R16 >>= cl D3/7
|
||||
I(SARrr32 , "sarl", 0xD3, 0, X86II::MRMS7r, O_CL, NoImpRegs) // R32 >>= cl D3/7
|
||||
I(SARir8 , "sarb", 0xC0, 0, X86II::MRMS7r, NoImpRegs, NoImpRegs) // R8 >>= imm8 C0/7 ib
|
||||
I(SARir16 , "sarw", 0xC1, 0, X86II::MRMS7r | X86II::OpSize, NoImpRegs, NoImpRegs) // R16 >>= imm8 C1/7 ib
|
||||
I(SARir32 , "sarl", 0xC1, 0, X86II::MRMS7r, NoImpRegs, NoImpRegs) // R32 >>= imm8 C1/7 ib
|
||||
|
||||
// Floating point loads
|
||||
I(FLDr4 , "flds", 0xD9, 0, X86II::MRMS0m) // push float D9/0
|
||||
I(FLDr8 , "fldl ", 0xDD, 0, X86II::MRMS0m) // push double DD/0
|
||||
I(FLDr4 , "flds", 0xD9, 0, X86II::MRMS0m, NoImpRegs, NoImpRegs) // push float D9/0
|
||||
I(FLDr8 , "fldl ", 0xDD, 0, X86II::MRMS0m, NoImpRegs, NoImpRegs) // push double DD/0
|
||||
|
||||
// Floating point compares
|
||||
I(FUCOMPP , "fucompp", 0xDA, 0, X86II::Void) // compare+pop2x DA E9
|
||||
I(FUCOMPP , "fucompp", 0xDA, 0, X86II::Void, NoImpRegs, NoImpRegs) // compare+pop2x DA E9
|
||||
|
||||
// Floating point flag ops
|
||||
I(FNSTSWr8 , "fnstsw", 0xDF, 0, X86II::Void) // AX = fp flags DF E0
|
||||
I(FNSTSWr8 , "fnstsw", 0xDF, 0, X86II::Void, NoImpRegs, O_AX) // AX = fp flags DF E0
|
||||
|
||||
// Condition code ops, incl. set if equal/not equal/...
|
||||
I(SAHF , "sahf", 0x9E, 0, X86II::RawFrm) // flags = AH
|
||||
I(SETBr , "setb", 0x92, 0, X86II::TB | X86II::MRMS0r) // R8 = < unsign
|
||||
I(SETAEr , "setae", 0x93, 0, X86II::TB | X86II::MRMS0r) // R8 = >=unsign
|
||||
I(SETEr , "sete", 0x94, 0, X86II::TB | X86II::MRMS0r) // R8 = ==
|
||||
I(SETNEr , "setne", 0x95, 0, X86II::TB | X86II::MRMS0r) // R8 = !=
|
||||
I(SETBEr , "setbe", 0x96, 0, X86II::TB | X86II::MRMS0r) // R8 = <=unsign
|
||||
I(SETAr , "seta", 0x97, 0, X86II::TB | X86II::MRMS0r) // R8 = > unsign
|
||||
I(SETLr , "setl", 0x9C, 0, X86II::TB | X86II::MRMS0r) // R8 = < signed
|
||||
I(SETGEr , "setge", 0x9D, 0, X86II::TB | X86II::MRMS0r) // R8 = >=signed
|
||||
I(SETLEr , "setle", 0x9E, 0, X86II::TB | X86II::MRMS0r) // R8 = <=signed
|
||||
I(SETGr , "setg", 0x9F, 0, X86II::TB | X86II::MRMS0r) // R8 = > signed
|
||||
I(SAHF , "sahf", 0x9E, 0, X86II::RawFrm, O_AH, NoImpRegs) // flags = AH
|
||||
I(SETBr , "setb", 0x92, 0, X86II::TB | X86II::MRMS0r, NoImpRegs, NoImpRegs) // R8 = < unsign
|
||||
I(SETAEr , "setae", 0x93, 0, X86II::TB | X86II::MRMS0r, NoImpRegs, NoImpRegs) // R8 = >=unsign
|
||||
I(SETEr , "sete", 0x94, 0, X86II::TB | X86II::MRMS0r, NoImpRegs, NoImpRegs) // R8 = ==
|
||||
I(SETNEr , "setne", 0x95, 0, X86II::TB | X86II::MRMS0r, NoImpRegs, NoImpRegs) // R8 = !=
|
||||
I(SETBEr , "setbe", 0x96, 0, X86II::TB | X86II::MRMS0r, NoImpRegs, NoImpRegs) // R8 = <=unsign
|
||||
I(SETAr , "seta", 0x97, 0, X86II::TB | X86II::MRMS0r, NoImpRegs, NoImpRegs) // R8 = > unsign
|
||||
I(SETLr , "setl", 0x9C, 0, X86II::TB | X86II::MRMS0r, NoImpRegs, NoImpRegs) // R8 = < signed
|
||||
I(SETGEr , "setge", 0x9D, 0, X86II::TB | X86II::MRMS0r, NoImpRegs, NoImpRegs) // R8 = >=signed
|
||||
I(SETLEr , "setle", 0x9E, 0, X86II::TB | X86II::MRMS0r, NoImpRegs, NoImpRegs) // R8 = <=signed
|
||||
I(SETGr , "setg", 0x9F, 0, X86II::TB | X86II::MRMS0r, NoImpRegs, NoImpRegs) // R8 = > signed
|
||||
|
||||
// Integer comparisons
|
||||
I(CMPrr8 , "cmpb", 0x38, 0, X86II::MRMDestReg) // compare R8,R8
|
||||
I(CMPrr16 , "cmpw", 0x39, 0, X86II::MRMDestReg | X86II::OpSize) // compare R16,R16
|
||||
I(CMPrr32 , "cmpl", 0x39, 0, X86II::MRMDestReg) // compare R32,R32
|
||||
I(CMPri8 , "cmp", 0x80, 0, X86II::MRMS7r) // compare R8, imm8
|
||||
I(CMPrr8 , "cmpb", 0x38, 0, X86II::MRMDestReg, NoImpRegs, NoImpRegs) // compare R8,R8
|
||||
I(CMPrr16 , "cmpw", 0x39, 0, X86II::MRMDestReg | X86II::OpSize, NoImpRegs, NoImpRegs) // compare R16,R16
|
||||
I(CMPrr32 , "cmpl", 0x39, 0, X86II::MRMDestReg, NoImpRegs, NoImpRegs) // compare R32,R32
|
||||
I(CMPri8 , "cmp", 0x80, 0, X86II::MRMS7r, NoImpRegs, NoImpRegs) // compare R8, imm8
|
||||
|
||||
// Sign extenders (first 3 are good for DIV/IDIV; the others are more general)
|
||||
I(CBW , "cbw", 0x98, 0, X86II::RawFrm) // AX = signext(AL)
|
||||
I(CWD , "cwd", 0x99, 0, X86II::RawFrm) // DX:AX = signext(AX)
|
||||
I(CDQ , "cdq", 0x99, 0, X86II::RawFrm) // EDX:EAX = signext(EAX)
|
||||
I(MOVSXr16r8 , "movsx", 0xBE, 0, X86II::MRMSrcReg | X86II::TB | // R16 = signext(R8)
|
||||
X86II::OpSize)
|
||||
I(MOVSXr32r8 , "movsx", 0xBE, 0, X86II::MRMSrcReg | X86II::TB) // R32 = signext(R8)
|
||||
I(MOVSXr32r16 , "movsx", 0xBF, 0, X86II::MRMSrcReg | X86II::TB) // R32 = signext(R16)
|
||||
I(CBW , "cbw", 0x98, 0, X86II::RawFrm, O_AL, O_AX) // AX = signext(AL)
|
||||
I(CWD , "cwd", 0x99, 0, X86II::RawFrm, O_AX, O_DX) // DX:AX = signext(AX)
|
||||
I(CDQ , "cdq", 0x99, 0, X86II::RawFrm, O_EAX, O_EDX) // EDX:EAX = signext(EAX)
|
||||
I(MOVSXr16r8 , "movsx", 0xBE, 0, X86II::MRMSrcReg | X86II::TB | // R16 = signext(R8)
|
||||
X86II::OpSize, NoImpRegs, NoImpRegs)
|
||||
I(MOVSXr32r8 , "movsx", 0xBE, 0, X86II::MRMSrcReg | X86II::TB, NoImpRegs, NoImpRegs) // R32 = signext(R8)
|
||||
I(MOVSXr32r16 , "movsx", 0xBF, 0, X86II::MRMSrcReg | X86II::TB, NoImpRegs, NoImpRegs) // R32 = signext(R16)
|
||||
I(MOVZXr16r8 , "movzx", 0xB6, 0, X86II::MRMSrcReg | X86II::TB | // R16 = zeroext(R8)
|
||||
X86II::OpSize)
|
||||
I(MOVZXr32r8 , "movzx", 0xB6, 0, X86II::MRMSrcReg | X86II::TB) // R32 = zeroext(R8)
|
||||
I(MOVZXr32r16 , "movzx", 0xB7, 0, X86II::MRMSrcReg | X86II::TB) // R32 = zeroext(R16)
|
||||
X86II::OpSize, NoImpRegs, NoImpRegs)
|
||||
I(MOVZXr32r8 , "movzx", 0xB6, 0, X86II::MRMSrcReg | X86II::TB, NoImpRegs, NoImpRegs) // R32 = zeroext(R8)
|
||||
I(MOVZXr32r16 , "movzx", 0xB7, 0, X86II::MRMSrcReg | X86II::TB, NoImpRegs, NoImpRegs) // R32 = zeroext(R16)
|
||||
|
||||
// At this point, I is dead, so undefine the macro
|
||||
#undef I
|
||||
|
||||
Loading…
Reference in New Issue
Block a user