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R600/SI: dynamical figure out the reg class of MIMG
Depending on the number of bits set in the writemask. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179166 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -107,6 +107,9 @@ void AMDGPUAsmPrinter::EmitProgramInfo(MachineFunction &MF) {
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} else if (AMDGPU::VReg_64RegClass.contains(reg)) {
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isSGPR = false;
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width = 2;
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} else if (AMDGPU::VReg_96RegClass.contains(reg)) {
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isSGPR = false;
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width = 3;
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} else if (AMDGPU::SReg_128RegClass.contains(reg)) {
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isSGPR = true;
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width = 4;
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@ -720,7 +720,7 @@ unsigned SubIdx2Lane(unsigned Idx) {
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void SITargetLowering::adjustWritemask(MachineSDNode *&Node,
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SelectionDAG &DAG) const {
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SDNode *Users[4] = { };
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unsigned Writemask = 0;
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unsigned Writemask = 0, Lane = 0;
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// Try to figure out the used register components
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for (SDNode::use_iterator I = Node->use_begin(), E = Node->use_end();
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@ -731,7 +731,7 @@ void SITargetLowering::adjustWritemask(MachineSDNode *&Node,
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I->getMachineOpcode() != TargetOpcode::EXTRACT_SUBREG)
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return;
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unsigned Lane = SubIdx2Lane(I->getConstantOperandVal(1));
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Lane = SubIdx2Lane(I->getConstantOperandVal(1));
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// Abort if we have more than one user per component
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if (Users[Lane])
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@ -752,6 +752,16 @@ void SITargetLowering::adjustWritemask(MachineSDNode *&Node,
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Ops.push_back(Node->getOperand(i));
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Node = (MachineSDNode*)DAG.UpdateNodeOperands(Node, Ops.data(), Ops.size());
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// If we only got one lane, replace it with a copy
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if (Writemask == (1U << Lane)) {
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SDValue RC = DAG.getTargetConstant(AMDGPU::VReg_32RegClassID, MVT::i32);
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SDNode *Copy = DAG.getMachineNode(TargetOpcode::COPY_TO_REGCLASS,
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DebugLoc(), MVT::f32,
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SDValue(Node, 0), RC);
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DAG.ReplaceAllUsesWith(Users[Lane], Copy);
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return;
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}
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// Update the users of the node with the new indices
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for (unsigned i = 0, Idx = AMDGPU::sub0; i < 4; ++i) {
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@ -780,3 +790,28 @@ SDNode *SITargetLowering::PostISelFolding(MachineSDNode *Node,
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return foldOperands(Node, DAG);
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}
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/// \brief Assign the register class depending on the number of
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/// bits set in the writemask
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void SITargetLowering::AdjustInstrPostInstrSelection(MachineInstr *MI,
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SDNode *Node) const {
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if (AMDGPU::isMIMG(MI->getOpcode()) == -1)
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return;
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unsigned VReg = MI->getOperand(0).getReg();
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unsigned Writemask = MI->getOperand(1).getImm();
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unsigned BitsSet = 0;
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for (unsigned i = 0; i < 4; ++i)
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BitsSet += Writemask & (1 << i) ? 1 : 0;
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const TargetRegisterClass *RC;
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switch (BitsSet) {
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default: return;
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case 1: RC = &AMDGPU::VReg_32RegClass; break;
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case 2: RC = &AMDGPU::VReg_64RegClass; break;
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case 3: RC = &AMDGPU::VReg_96RegClass; break;
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}
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MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
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MRI.setRegClass(VReg, RC);
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}
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@ -53,6 +53,8 @@ public:
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virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
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virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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virtual SDNode *PostISelFolding(MachineSDNode *N, SelectionDAG &DAG) const;
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virtual void AdjustInstrPostInstrSelection(MachineInstr *MI,
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SDNode *Node) const;
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int32_t analyzeImmediate(const SDNode *N) const;
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};
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@ -58,6 +58,10 @@ SIInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
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AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3, 0
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};
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const int16_t Sub0_2[] = {
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AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, 0
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};
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const int16_t Sub0_1[] = {
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AMDGPU::sub0, AMDGPU::sub1, 0
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};
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@ -125,6 +129,11 @@ SIInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
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Opcode = AMDGPU::V_MOV_B32_e32;
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SubIndices = Sub0_1;
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} else if (AMDGPU::VReg_96RegClass.contains(DestReg)) {
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assert(AMDGPU::VReg_96RegClass.contains(SrcReg));
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Opcode = AMDGPU::V_MOV_B32_e32;
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SubIndices = Sub0_2;
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} else if (AMDGPU::VReg_128RegClass.contains(DestReg)) {
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assert(AMDGPU::VReg_128RegClass.contains(SrcReg) ||
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AMDGPU::SReg_128RegClass.contains(SrcReg));
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@ -346,6 +346,7 @@ class MIMG_Load_Helper <bits<7> op, string asm> : MIMG <
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[]> {
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let mayLoad = 1;
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let mayStore = 0;
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let hasPostISelHook = 1;
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}
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//===----------------------------------------------------------------------===//
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@ -379,6 +380,7 @@ def getCommuteOrig : InstrMapping {
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let ValueCols = [["1"]];
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}
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// Test if the supplied opcode is an MIMG instruction
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def isMIMG : InstrMapping {
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let FilterClass = "MIMG_Load_Helper";
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let RowFields = ["Inst"];
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@ -94,6 +94,12 @@ def VGPR_64 : RegisterTuples<[sub0, sub1],
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[(add (trunc VGPR_32, 255)),
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(add (shl VGPR_32, 1))]>;
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// VGPR 96-bit registers
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def VGPR_96 : RegisterTuples<[sub0, sub1, sub2],
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[(add (trunc VGPR_32, 254)),
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(add (shl VGPR_32, 1)),
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(add (shl VGPR_32, 2))]>;
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// VGPR 128-bit registers
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def VGPR_128 : RegisterTuples<[sub0, sub1, sub2, sub3],
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[(add (trunc VGPR_32, 253)),
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@ -162,6 +168,10 @@ def VReg_32 : RegisterClass<"AMDGPU", [i32, f32, v1i32], 32, (add VGPR_32)>;
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def VReg_64 : RegisterClass<"AMDGPU", [i64, f64, v2i32, v2f32], 64, (add VGPR_64)>;
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def VReg_96 : RegisterClass<"AMDGPU", [untyped], 96, (add VGPR_96)> {
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let Size = 96;
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}
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def VReg_128 : RegisterClass<"AMDGPU", [v4i32, v4f32], 128, (add VGPR_128)>;
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def VReg_256 : RegisterClass<"AMDGPU", [v8i32, v8f32], 256, (add VGPR_256)>;
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@ -1,21 +1,21 @@
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;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck %s
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;CHECK: IMAGE_SAMPLE {{VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+}}, 15
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;CHECK: IMAGE_SAMPLE {{VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+}}, 3
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;CHECK: IMAGE_SAMPLE {{VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+}}, 2
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;CHECK: IMAGE_SAMPLE {{VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+}}, 1
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;CHECK: IMAGE_SAMPLE {{VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+}}, 4
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;CHECK: IMAGE_SAMPLE {{VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+}}, 8
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;CHECK: IMAGE_SAMPLE_C {{VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+}}, 5
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;CHECK: IMAGE_SAMPLE_C {{VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+}}, 9
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;CHECK: IMAGE_SAMPLE_C {{VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+}}, 6
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;CHECK: IMAGE_SAMPLE {{VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+}}, 10
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;CHECK: IMAGE_SAMPLE {{VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+}}, 12
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;CHECK: IMAGE_SAMPLE_C {{VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+}}, 7
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;CHECK: IMAGE_SAMPLE_C {{VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+}}, 11
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;CHECK: IMAGE_SAMPLE_C {{VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+}}, 13
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;CHECK: IMAGE_SAMPLE {{VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+}}, 14
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;CHECK: IMAGE_SAMPLE {{VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+}}, 8
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;CHECK: IMAGE_SAMPLE {{VGPR[0-9]+_VGPR[0-9]+}}, 3
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;CHECK: IMAGE_SAMPLE {{VGPR[0-9]+}}, 2
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;CHECK: IMAGE_SAMPLE {{VGPR[0-9]+}}, 1
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;CHECK: IMAGE_SAMPLE {{VGPR[0-9]+}}, 4
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;CHECK: IMAGE_SAMPLE {{VGPR[0-9]+}}, 8
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;CHECK: IMAGE_SAMPLE_C {{VGPR[0-9]+_VGPR[0-9]+}}, 5
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;CHECK: IMAGE_SAMPLE_C {{VGPR[0-9]+_VGPR[0-9]+}}, 9
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;CHECK: IMAGE_SAMPLE_C {{VGPR[0-9]+_VGPR[0-9]+}}, 6
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;CHECK: IMAGE_SAMPLE {{VGPR[0-9]+_VGPR[0-9]+}}, 10
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;CHECK: IMAGE_SAMPLE {{VGPR[0-9]+_VGPR[0-9]+}}, 12
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;CHECK: IMAGE_SAMPLE_C {{VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+}}, 7
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;CHECK: IMAGE_SAMPLE_C {{VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+}}, 11
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;CHECK: IMAGE_SAMPLE_C {{VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+}}, 13
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;CHECK: IMAGE_SAMPLE {{VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+}}, 14
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;CHECK: IMAGE_SAMPLE {{VGPR[0-9]+}}, 8
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define void @test(i32 %a1, i32 %a2, i32 %a3, i32 %a4) {
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%v1 = insertelement <4 x i32> undef, i32 %a1, i32 0
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