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Add some more comments about checkings of invalid register numbers.

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And two test cases.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129090 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Johnny Chen 2011-04-07 18:33:19 +00:00
parent 45e1a53efd
commit 4d4e25740b
3 changed files with 19 additions and 0 deletions
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5
lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
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@ -1110,6 +1110,11 @@ static bool DisassembleDPSoRegFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
// A8.6.3 ADC (register-shifted register)
// if d == 15 || n == 15 || m == 15 || s == 15 then UNPREDICTABLE;
//
// This also accounts for shift instructions (register) where, fortunately,
// Inst{19-16} = 0b0000.
// A8.6.89 LSL (register)
// if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;
if (decodeRd(insn) == 15 || decodeRn(insn) == 15 ||
decodeRm(insn) == 15 || decodeRs(insn) == 15)
return false;

3
test/MC/Disassembler/ARM/arm-tests.txt
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@ -245,3 +245,6 @@
# CHECK: smlsldx r4, r12, r11, r4
0x7b 0x44 0x4c 0xe7
# CHECK: lsl r3, r2, r1
0x12 0x31 0xa0 0xe1

11
test/MC/Disassembler/ARM/invalid-LSL-regform.txt Normal file
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@ -0,0 +1,11 @@
# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding}
# Opcode=196 Name=MOVs Format=ARM_FORMAT_DPSOREGFRM(5)
# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
# -------------------------------------------------------------------------------------------------
# | 1: 1: 1: 0| 0: 0: 0: 1| 1: 0: 1: 0| 0: 0: 0: 0| 1: 1: 1: 1| 0: 0: 0: 1| 0: 0: 0: 1| 0: 0: 1: 0|
# -------------------------------------------------------------------------------------------------
#
# A8.6.89 LSL (register)
# if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;
0x12 0xf1 0xa0 0xe1