6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-11-01 15:11:24 +00:00
Code Issues Projects Releases Wiki Activity

A8.6.92 MCR (Encoding A1): if coproc == '101x' then SEE "Advanced SIMD and VFP"

Browse Source 
Since these "Advanced SIMD and VFP" instructions have more specfic encoding bits
specified, if coproc == 10 or 11, we should reject the insn as invalid.

rdar://problem/9239922
rdar://problem/9239596


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129027 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Johnny Chen 2011-04-06 20:49:02 +00:00
parent a040d47c74
commit 4d81c9a6ba
4 changed files with 30 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

15
lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
View File

@ -686,8 +686,21 @@ static bool DisassembleCoprocessor(MCInst &MI, unsigned Opcode, uint32_t insn,
assert(NumOps >= 4 && "Num of operands >= 4 for coprocessor instr");
unsigned &OpIdx = NumOpsAdded;
// A8.6.92
// if coproc == '101x' then SEE "Advanced SIMD and VFP"
// But since the special instructions have more explicit encoding bits
// specified, if coproc == 10 or 11, we should reject it as invalid.
unsigned coproc = GetCoprocessor(insn);
if ((Opcode == ARM::MCR || Opcode == ARM::MCRR ||
Opcode == ARM::MRC || Opcode == ARM::MRRC) &&
(coproc == 10 || coproc == 11)) {
DEBUG(errs() << "Encoding error: coproc == 10 or 11 for MCR[R]/MR[R]C\n");
return false;
}
bool OneCopOpc = (Opcode == ARM::MCRR || Opcode == ARM::MCRR2 ||
Opcode == ARM::MRRC || Opcode == ARM::MRRC2);
// CDP/CDP2 has no GPR operand; the opc1 operand is also wider (Inst{23-20}).
bool NoGPR = (Opcode == ARM::CDP || Opcode == ARM::CDP2);
bool LdStCop = LdStCopOpcode(Opcode);
@ -700,7 +713,7 @@ static bool DisassembleCoprocessor(MCInst &MI, unsigned Opcode, uint32_t insn,
decodeRd(insn))));
++OpIdx;
}
MI.addOperand(MCOperand::CreateImm(GetCoprocessor(insn)));
MI.addOperand(MCOperand::CreateImm(coproc));
++OpIdx;
if (LdStCop) {

10
test/MC/Disassembler/ARM/invalid-MCR-arm.txt Normal file
View File

@ -0,0 +1,10 @@
# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding}
# Opcode=171 Name=MCR Format=ARM_FORMAT_BRFRM(2)
# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
# -------------------------------------------------------------------------------------------------
# | 0: 0: 1: 0| 1: 1: 1: 0| 1: 0: 1: 0| 0: 0: 0: 0| 0: 0: 0: 1| 1: 0: 1: 1| 0: 0: 0: 1| 1: 0: 1: 1|
# -------------------------------------------------------------------------------------------------
#
# Encoding error: coproc == 10 or 11 for MCR[R]/MR[R]C
0x1b 0x1b 0xa0 0x2e

3
test/MC/Disassembler/ARM/neon-tests.txt
View File

@ -74,3 +74,6 @@
# CHECK: vmov.s8 r0, d8[1]
0x30 0x0b 0x58 0xee
# CHECK: vmov r1, r0, d11
0x1b 0x1b 0x50 0xec

3
test/MC/Disassembler/ARM/thumb-tests.txt
View File

@ -199,3 +199,6 @@
# CHECK: stc2 p12, cr15, [r9], {137}
0x89 0xfc 0x89 0xfc
# CHECK: vmov r1, r0, d11
0x50 0xec 0x1b 0x1b