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Eliminate sub_ss, sub_sd from broadcast patterns.
The (COPY_TO_REGCLASS GR32:$src, VR128) pattern looks odd, but copyPhysReg does the right thing with it. (The old pattern would eventually produce the same cross-class copy). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160830 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -7704,24 +7704,18 @@ let Predicates = [HasAVX2] in {
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// is used by additional users, which prevents the pattern selection.
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let AddedComplexity = 20 in {
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def : Pat<(v4f32 (X86VBroadcast FR32:$src)),
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(VBROADCASTSSrr
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(INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src, sub_ss))>;
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(VBROADCASTSSrr (COPY_TO_REGCLASS FR32:$src, VR128))>;
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def : Pat<(v8f32 (X86VBroadcast FR32:$src)),
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(VBROADCASTSSYrr
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(INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src, sub_ss))>;
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(VBROADCASTSSYrr (COPY_TO_REGCLASS FR32:$src, VR128))>;
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def : Pat<(v4f64 (X86VBroadcast FR64:$src)),
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(VBROADCASTSDYrr
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(INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src, sub_sd))>;
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(VBROADCASTSDYrr (COPY_TO_REGCLASS FR64:$src, VR128))>;
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def : Pat<(v4i32 (X86VBroadcast GR32:$src)),
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(VBROADCASTSSrr
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(INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), GR32:$src, sub_ss))>;
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(VBROADCASTSSrr (COPY_TO_REGCLASS GR32:$src, VR128))>;
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def : Pat<(v8i32 (X86VBroadcast GR32:$src)),
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(VBROADCASTSSYrr
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(INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), GR32:$src, sub_ss))>;
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(VBROADCASTSSYrr (COPY_TO_REGCLASS GR32:$src, VR128))>;
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def : Pat<(v4i64 (X86VBroadcast GR64:$src)),
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(VBROADCASTSDYrr
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(INSERT_SUBREG (v2i64 (IMPLICIT_DEF)), GR64:$src, sub_sd))>;
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(VBROADCASTSDYrr (COPY_TO_REGCLASS GR64:$src, VR128))>;
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}
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}
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@ -7745,46 +7739,26 @@ def : Pat<(v4i32 (X86VBroadcast (loadi32 addr:$src))),
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let AddedComplexity = 20 in {
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// 128bit broadcasts:
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def : Pat<(v4f32 (X86VBroadcast FR32:$src)),
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(VPSHUFDri
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(INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src, sub_ss), 0)>;
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(VPSHUFDri (COPY_TO_REGCLASS FR32:$src, VR128), 0)>;
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def : Pat<(v8f32 (X86VBroadcast FR32:$src)),
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(VINSERTF128rr (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)),
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(VPSHUFDri
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(INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src, sub_ss), 0),
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sub_xmm),
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(VPSHUFDri
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(INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src, sub_ss),
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0), 1)>;
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(VPSHUFDri (COPY_TO_REGCLASS FR32:$src, VR128), 0), sub_xmm),
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(VPSHUFDri (COPY_TO_REGCLASS FR32:$src, VR128), 0), 1)>;
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def : Pat<(v4f64 (X86VBroadcast FR64:$src)),
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(VINSERTF128rr (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)),
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(VPSHUFDri
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(INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src, sub_sd),
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0x44),
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sub_xmm),
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(VPSHUFDri
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(INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src, sub_sd),
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0x44), 1)>;
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(VPSHUFDri (COPY_TO_REGCLASS FR64:$src, VR128), 0x44), sub_xmm),
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(VPSHUFDri (COPY_TO_REGCLASS FR64:$src, VR128), 0x44), 1)>;
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def : Pat<(v4i32 (X86VBroadcast GR32:$src)),
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(VPSHUFDri
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(INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), GR32:$src, sub_ss), 0)>;
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(VPSHUFDri (COPY_TO_REGCLASS GR32:$src, VR128), 0)>;
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def : Pat<(v8i32 (X86VBroadcast GR32:$src)),
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(VINSERTF128rr (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)),
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(VPSHUFDri
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(INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), GR32:$src, sub_ss), 0),
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sub_xmm),
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(VPSHUFDri
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(INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), GR32:$src, sub_ss),
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0), 1)>;
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(VPSHUFDri (COPY_TO_REGCLASS GR32:$src, VR128), 0), sub_xmm),
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(VPSHUFDri (COPY_TO_REGCLASS GR32:$src, VR128), 0), 1)>;
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def : Pat<(v4i64 (X86VBroadcast GR64:$src)),
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(VINSERTF128rr (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)),
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(VPSHUFDri
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(INSERT_SUBREG (v2i64 (IMPLICIT_DEF)), GR64:$src, sub_sd),
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0x44),
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sub_xmm),
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(VPSHUFDri
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(INSERT_SUBREG (v2i64 (IMPLICIT_DEF)), GR64:$src, sub_sd),
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0x44), 1)>;
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(VPSHUFDri (COPY_TO_REGCLASS GR64:$src, VR128), 0x44), sub_xmm),
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(VPSHUFDri (COPY_TO_REGCLASS GR64:$src, VR128), 0x44), 1)>;
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}
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}
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