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Replace some bit operations with simpler ones. No functionality change.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182226 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Benjamin Kramer
2013-05-19 22:01:57 +00:00
parent 634123e98d
commit 4dc8bdf87d
3 changed files with 9 additions and 12 deletions
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2
lib/Target/ARM/Disassembler/ARMDisassembler.cpp
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@ -1224,7 +1224,7 @@ static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val,
}
// Empty register lists are not allowed.
if (CountPopulation_32(Val) == 0) return MCDisassembler::Fail;
if (Val == 0) return MCDisassembler::Fail;
for (unsigned i = 0; i < 16; ++i) {
if (Val & (1 << i)) {
if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder)))