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Fix bug where ReduceLoadWidth was creating illegal ZEXTLOAD instructions.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124587 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Richard Osborne 2011-01-31 17:41:44 +00:00
parent e85dcb54d1
commit 4e3740ee6d
2 changed files with 12 additions and 2 deletions
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4
lib/CodeGen/SelectionDAG/DAGCombiner.cpp
View File

@ -4244,8 +4244,6 @@ SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) {
if (Opc == ISD::SIGN_EXTEND_INREG) {
ExtType = ISD::SEXTLOAD;
ExtVT = cast<VTSDNode>(N->getOperand(1))->getVT();
if (LegalOperations && !TLI.isLoadExtLegal(ISD::SEXTLOAD, ExtVT))
return SDValue();
} else if (Opc == ISD::SRL) {
// Another special-case: SRL is basically zero-extending a narrower value.
ExtType = ISD::ZEXTLOAD;
@ -4255,6 +4253,8 @@ SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) {
ExtVT = EVT::getIntegerVT(*DAG.getContext(),
VT.getSizeInBits() - N01->getZExtValue());
}
if (LegalOperations && !TLI.isLoadExtLegal(ExtType, ExtVT))
return SDValue();
unsigned EVTBits = ExtVT.getSizeInBits();

10
test/CodeGen/XCore/2011-01-31-DAGCombineBug.ll Normal file
View File

@ -0,0 +1,10 @@
; RUN: llc < %s -march=xcore
%struct.st = type <{ i8, i32, i8, i32, i8, i32 }>
@x = external global %struct.st, align 4
define i32 @test_entry() nounwind {
entry:
%0 = load i32* getelementptr inbounds (%struct.st* @x, i32 0, i32 3), align 2
ret i32 %0
}