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scavenged frame index value re-use gets confused when more than one base
register is involved for thumb1. Work around this for the moment by only re-using SP-relative offsets. This is temporary 'til the code can distinguish multiple base registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98071 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -40,7 +40,7 @@
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#include "llvm/Support/CommandLine.h"
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using namespace llvm;
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static cl::opt<bool>
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cl::opt<bool>
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ReuseFrameIndexVals("arm-reuse-frame-index-vals", cl::Hidden, cl::init(true),
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cl::desc("Reuse repeated frame index values"));
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@ -33,10 +33,13 @@
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/ADT/BitVector.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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extern cl::opt<bool> ReuseFrameIndexVals;
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Thumb1RegisterInfo::Thumb1RegisterInfo(const ARMBaseInstrInfo &tii,
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const ARMSubtarget &sti)
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: ARMBaseRegisterInfo(tii, sti) {
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@ -640,6 +643,7 @@ Thumb1RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
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assert (Value && "Frame index virtual allocated, but Value arg is NULL!");
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*Value = Offset;
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bool UseRR = false;
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bool TrackVReg = FrameReg == ARM::SP;
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if (Opcode == ARM::tSpill) {
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if (FrameReg == ARM::SP)
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@ -648,6 +652,7 @@ Thumb1RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
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else {
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emitLoadConstPool(MBB, II, dl, VReg, 0, Offset);
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UseRR = true;
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TrackVReg = false;
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}
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} else
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emitThumbRegPlusImmediate(MBB, II, VReg, FrameReg, Offset, TII,
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@ -658,6 +663,8 @@ Thumb1RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
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MI.addOperand(MachineOperand::CreateReg(FrameReg, false));
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else // tSTR has an extra register operand.
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MI.addOperand(MachineOperand::CreateReg(0, false));
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if (!ReuseFrameIndexVals || !TrackVReg)
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VReg = 0;
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} else
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assert(false && "Unexpected opcode!");
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