mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-14 11:32:34 +00:00
Let's see if we can break things.
Lower GOT relative addresses to Lo and HI. Update both ISels to select them when they can. Saves instructions here and there. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25001 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Andrew Lenharth
parent
9fa4d4c7c4
commit
4e62951282
@ -203,13 +203,16 @@ SDOperand AlphaDAGToDAGISel::Select(SDOperand Op) {
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CurDAG->getTargetFrameIndex(FI, MVT::i32),
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getI64Imm(0));
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}
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case ISD::ConstantPool: {
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case AlphaISD::GlobalBaseReg:
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return getGlobalBaseReg();
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case ISD::TargetConstantPool: {
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Constant *C = cast<ConstantPoolSDNode>(N)->get();
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SDOperand Tmp, CPI = CurDAG->getTargetConstantPool(C, MVT::i64);
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Tmp = CurDAG->getTargetNode(Alpha::LDAHr, MVT::i64, CPI, getGlobalBaseReg());
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return CurDAG->SelectNodeTo(N, Alpha::LDAr, MVT::i64, CPI, Tmp);
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}
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case ISD::GlobalAddress: {
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case ISD::TargetGlobalAddress: {
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GlobalValue *GV = cast<GlobalAddressSDNode>(N)->getGlobal();
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SDOperand GA = CurDAG->getTargetGlobalAddress(GV, MVT::i64);
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return CurDAG->SelectNodeTo(N, Alpha::LDQl, MVT::i64, GA,
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@ -104,6 +104,11 @@ AlphaTargetLowering::AlphaTargetLowering(TargetMachine &TM) : TargetLowering(TM)
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setOperationAction(ISD::LOCATION, MVT::Other, Expand);
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setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
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// We want to legalize GlobalAddress and ConstantPool nodes into the
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// appropriate instructions to materialize the address.
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setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
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setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
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addLegalFPImmediate(+0.0); //F31
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addLegalFPImmediate(-0.0); //-F31
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@ -434,6 +439,28 @@ SDOperand AlphaTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
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return DAG.getLoad(MVT::i64, ST, FI, DAG.getSrcValue(0));
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}
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}
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case ISD::ConstantPool: {
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Constant *C = cast<ConstantPoolSDNode>(Op)->get();
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SDOperand CPI = DAG.getTargetConstantPool(C, MVT::i64);
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SDOperand Hi = DAG.getNode(AlphaISD::GPRelHi, MVT::i64, CPI,
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DAG.getNode(AlphaISD::GlobalBaseReg, MVT::i64));
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SDOperand Lo = DAG.getNode(AlphaISD::GPRelLo, MVT::i64, CPI, Hi);
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return Lo;
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}
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case ISD::GlobalAddress: {
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GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
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GlobalValue *GV = GSDN->getGlobal();
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SDOperand GA = DAG.getTargetGlobalAddress(GV, MVT::i64, GSDN->getOffset());
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if (!GV->hasWeakLinkage() && !GV->isExternal()) {
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SDOperand Hi = DAG.getNode(AlphaISD::GPRelHi, MVT::i64, GA,
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DAG.getNode(AlphaISD::GlobalBaseReg, MVT::i64));
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SDOperand Lo = DAG.getNode(AlphaISD::GPRelLo, MVT::i64, GA, Hi);
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return Lo;
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} else
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return GA;
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}
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}
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@ -27,6 +27,18 @@ namespace llvm {
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FIRST_NUMBER = ISD::BUILTIN_OP_END+Alpha::INSTRUCTION_LIST_END,
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//These corrospond to the identical Instruction
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ITOFT_, FTOIT_, CVTQT_, CVTQS_, CVTTQ_,
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/// GPRelHi/GPRelLo - These represent the high and low 16-bit
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/// parts of a global address respectively. These nodes have
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/// two operands, the first of which must be a
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/// TargetGlobalAddress, and the second of which must be a
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/// Constant. Selected naively, these turn into 'ldah R(G)' and
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/// 'lda R(C)', though these are usually folded into other nodes.
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GPRelHi, GPRelLo,
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/// GlobalBaseReg, used to restore the GOT ptr
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GlobalBaseReg,
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};
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}
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@ -676,31 +676,26 @@ unsigned AlphaISel::SelectExpr(SDOperand N) {
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getValueInfo(dyn_cast<SrcValueSDNode>(N.getOperand(2))->getValue(),
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i, j, k);
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GlobalAddressSDNode *GASD = dyn_cast<GlobalAddressSDNode>(Address);
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if (GASD && !GASD->getGlobal()->isExternal()) {
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Tmp1 = MakeReg(MVT::i64);
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AlphaLowering.restoreGP(BB);
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BuildMI(BB, Alpha::LDAHr, 2, Tmp1)
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.addGlobalAddress(GASD->getGlobal()).addReg(Alpha::R29);
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if (EnableAlphaLSMark)
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BuildMI(BB, Alpha::MEMLABEL, 4).addImm(i).addImm(j).addImm(k)
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.addImm(getUID());
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BuildMI(BB, GetRelVersion(Opc), 2, Result)
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.addGlobalAddress(GASD->getGlobal()).addReg(Tmp1);
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} else if (ConstantPoolSDNode *CP =
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dyn_cast<ConstantPoolSDNode>(Address)) {
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unsigned CPIdx = BB->getParent()->getConstantPool()->
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getConstantPoolIndex(CP->get());
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AlphaLowering.restoreGP(BB);
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has_sym = true;
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Tmp1 = MakeReg(MVT::i64);
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BuildMI(BB, Alpha::LDAHr, 2, Tmp1).addConstantPoolIndex(CPIdx)
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.addReg(Alpha::R29);
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if (EnableAlphaLSMark)
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BuildMI(BB, Alpha::MEMLABEL, 4).addImm(i).addImm(j).addImm(k)
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.addImm(getUID());
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BuildMI(BB, GetRelVersion(Opc), 2, Result)
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.addConstantPoolIndex(CPIdx).addReg(Tmp1);
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if (Address.getOpcode() == AlphaISD::GPRelLo) {
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unsigned Hi = SelectExpr(Address.getOperand(1));
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Address = Address.getOperand(0);
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if (GlobalAddressSDNode *GASD = dyn_cast<GlobalAddressSDNode>(Address)) {
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if (EnableAlphaLSMark)
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BuildMI(BB, Alpha::MEMLABEL, 4).addImm(i).addImm(j).addImm(k)
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.addImm(getUID());
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BuildMI(BB, GetRelVersion(Opc), 2, Result)
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.addGlobalAddress(GASD->getGlobal()).addReg(Hi);
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} else if (ConstantPoolSDNode *CP =
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dyn_cast<ConstantPoolSDNode>(Address)) {
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unsigned CPIdx = BB->getParent()->getConstantPool()->
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getConstantPoolIndex(CP->get());
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has_sym = true;
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if (EnableAlphaLSMark)
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BuildMI(BB, Alpha::MEMLABEL, 4).addImm(i).addImm(j).addImm(k)
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.addImm(getUID());
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BuildMI(BB, GetRelVersion(Opc), 2, Result)
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.addConstantPoolIndex(CPIdx).addReg(Tmp1);
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} else assert(0 && "Unknown Lo part");
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} else if(Address.getOpcode() == ISD::FrameIndex) {
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if (EnableAlphaLSMark)
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BuildMI(BB, Alpha::MEMLABEL, 4).addImm(i).addImm(j).addImm(k)
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@ -718,6 +713,36 @@ unsigned AlphaISel::SelectExpr(SDOperand N) {
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}
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return Result;
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}
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case AlphaISD::GlobalBaseReg:
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AlphaLowering.restoreGP(BB);
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BuildMI(BB, Alpha::BIS, 2, Result).addReg(Alpha::R29).addReg(Alpha::R29);
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return Result;
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case AlphaISD::GPRelHi:
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if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(N.getOperand(0)))
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BuildMI(BB, Alpha::LDAHr, 2, Result)
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.addConstantPoolIndex(BB->getParent()->getConstantPool()->
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getConstantPoolIndex(CP->get()))
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.addReg(SelectExpr(N.getOperand(1)));
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else if (GlobalAddressSDNode *GASD =
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dyn_cast<GlobalAddressSDNode>(N.getOperand(0)))
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BuildMI(BB, Alpha::LDAHr, 2, Result)
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.addGlobalAddress(GASD->getGlobal())
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.addReg(SelectExpr(N.getOperand(1)));
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else assert(0 && "unknown Hi part");
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return Result;
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case AlphaISD::GPRelLo:
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if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(N.getOperand(0)))
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BuildMI(BB, Alpha::LDAr, 2, Result)
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.addConstantPoolIndex(BB->getParent()->getConstantPool()->
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getConstantPoolIndex(CP->get()))
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.addReg(SelectExpr(N.getOperand(1)));
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else if (GlobalAddressSDNode *GASD =
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dyn_cast<GlobalAddressSDNode>(N.getOperand(0)))
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BuildMI(BB, Alpha::LDAr, 2, Result)
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.addGlobalAddress(GASD->getGlobal())
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.addReg(SelectExpr(N.getOperand(1)));
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else assert(0 && "unknown Lo part");
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return Result;
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case ISD::GlobalAddress:
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AlphaLowering.restoreGP(BB);
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@ -1699,17 +1724,16 @@ void AlphaISel::Select(SDOperand N) {
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getValueInfo(cast<SrcValueSDNode>(N.getOperand(3))->getValue(),
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i, j, k);
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GlobalAddressSDNode *GASD = dyn_cast<GlobalAddressSDNode>(Address);
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if (GASD && !GASD->getGlobal()->isExternal()) {
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Tmp2 = MakeReg(MVT::i64);
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AlphaLowering.restoreGP(BB);
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BuildMI(BB, Alpha::LDAHr, 2, Tmp2)
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.addGlobalAddress(GASD->getGlobal()).addReg(Alpha::R29);
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if (EnableAlphaLSMark)
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BuildMI(BB, Alpha::MEMLABEL, 4).addImm(i).addImm(j).addImm(k)
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.addImm(getUID());
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BuildMI(BB, GetRelVersion(Opc), 3).addReg(Tmp1)
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.addGlobalAddress(GASD->getGlobal()).addReg(Tmp2);
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if (Address.getOpcode() == AlphaISD::GPRelLo) {
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unsigned Hi = SelectExpr(Address.getOperand(1));
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Address = Address.getOperand(0);
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if (GlobalAddressSDNode *GASD = dyn_cast<GlobalAddressSDNode>(Address)) {
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if (EnableAlphaLSMark)
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BuildMI(BB, Alpha::MEMLABEL, 4).addImm(i).addImm(j).addImm(k)
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.addImm(getUID());
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BuildMI(BB, GetRelVersion(Opc), 3).addReg(Tmp1)
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.addGlobalAddress(GASD->getGlobal()).addReg(Hi);
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} else assert(0 && "Unknown Lo part");
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} else if(Address.getOpcode() == ISD::FrameIndex) {
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if (EnableAlphaLSMark)
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BuildMI(BB, Alpha::MEMLABEL, 4).addImm(i).addImm(j).addImm(k)
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@ -25,6 +25,8 @@ def Alpha_ftoit : SDNode<"AlphaISD::FTOIT_", SDTFPToIntOp, []>;
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def Alpha_cvtqt : SDNode<"AlphaISD::CVTQT_", SDTFPUnaryOpUnC, []>;
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def Alpha_cvtqs : SDNode<"AlphaISD::CVTQS_", SDTFPUnaryOpUnC, []>;
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def Alpha_cvttq : SDNode<"AlphaISD::CVTTQ_", SDTFPUnaryOp, []>;
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def Alpha_gprello : SDNode<"AlphaISD::GPRelLo", SDTIntBinOp, []>;
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def Alpha_gprelhi : SDNode<"AlphaISD::GPRelHi", SDTIntBinOp, []>;
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// These are target-independent nodes, but have target-specific formats.
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def SDT_AlphaCallSeq : SDTypeProfile<0, 1, [ SDTCisVT<0, i64> ]>;
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@ -437,7 +439,8 @@ def BR : BForm<0x30, "br $RA,$DISP">; //Branch
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def BR_DAG : BFormD<0x30, "br $$31,$DISP">; //Branch
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let isLoad = 1, OperandList = (ops GPRC:$RA, GPRC:$RB), disp = 0 in {
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let OperandList = (ops GPRC:$RA, GPRC:$RB), disp = 0 in {
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let isLoad = 1 in {
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def LDQdag : MFormD<0x29, "ldq $RA,0($RB)",
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[(set GPRC:$RA, (load GPRC:$RB))]>;
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def LDLdag : MFormD<0x29, "ldl $RA,0($RB)",
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@ -446,7 +449,8 @@ def LDBUdag : MFormD<0x0A, "ldbu $RA,0($RB)",
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[(set GPRC:$RA, (zextload GPRC:$RB, i8))]>;
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def LDWUdag : MFormD<0x0C, "ldwu $RA,0($RB)",
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[(set GPRC:$RA, (zextload GPRC:$RB, i16))]>;
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}
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let isStore = 1 in {
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def STBdag : MFormD<0x0E, "stb $RA,0($RB)",
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[(truncstore GPRC:$RA, GPRC:$RB, i8)]>;
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def STWdag : MFormD<0x0D, "stw $RA,0($RB)",
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@ -456,6 +460,7 @@ def STLdag : MFormD<0x2C, "stl $RA,0($RB)",
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def STQdag : MFormD<0x2D, "stq $RA,0($RB)",
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[(store GPRC:$RA, GPRC:$RB)]>;
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}
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}
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def : Pat<(i64 (extload GPRC:$src, i8)),
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(LDBUdag GPRC:$src)>;
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@ -464,48 +469,56 @@ def : Pat<(i64 (extload GPRC:$src, i16)),
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def : Pat<(i64 (extload GPRC:$src, i32)),
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(LDLdag GPRC:$src)>;
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let isLoad = 1, OperandList = (ops F4RC:$RA, GPRC:$RB), disp = 0 in {
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let OperandList = (ops F4RC:$RA, GPRC:$RB), disp = 0 in {
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let isStore = 1 in
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def STSdag : MFormD<0x26, "sts $RA,0($RB)",
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[(store F4RC:$RA, GPRC:$RB)]>;
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let isLoad = 1 in
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def LDSdag : MFormD<0x22, "lds $RA,0($RB)",
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[(set F4RC:$RA, (load GPRC:$RB))]>;
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}
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let isLoad = 1, OperandList = (ops F8RC:$RA, GPRC:$RB), disp = 0 in {
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let OperandList = (ops F8RC:$RA, GPRC:$RB), disp = 0 in {
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let isStore = 1 in
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def STTdag : MFormD<0x27, "stt $RA,0($RB)",
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[(store F8RC:$RA, GPRC:$RB)]>;
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let isLoad = 1 in
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def LDTdag : MFormD<0x23, "ldt $RA,0($RB)",
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[(set F8RC:$RA, (load GPRC:$RB))]>;
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}
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let isStore = 1 in {
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//Stores, int
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def STB : MForm<0x0E, "stb $RA,$DISP($RB)">; // Store byte
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def STW : MForm<0x0D, "stw $RA,$DISP($RB)">; // Store word
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def STL : MForm<0x2C, "stl $RA,$DISP($RB)">; // Store longword
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def STQ : MForm<0x2D, "stq $RA,$DISP($RB)">; //Store quadword
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//Stores, float
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let OperandList = (ops F4RC:$RA, s16imm:$DISP, GPRC:$RB) in
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def STS : MFormAlt<0x26, "sts $RA,$DISP($RB)">; //Store S_floating
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let OperandList = (ops F8RC:$RA, s16imm:$DISP, GPRC:$RB) in
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def STT : MFormAlt<0x27, "stt $RA,$DISP($RB)">; //Store T_floating
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}
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let isLoad = 1 in {
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//Loads, int
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def LDL : MForm<0x28, "ldl $RA,$DISP($RB)">; // Load sign-extended longword
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def LDQ : MForm<0x29, "ldq $RA,$DISP($RB)">; //Load quadword
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def LDBU : MForm<0x0A, "ldbu $RA,$DISP($RB)">; //Load zero-extended byte
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def LDWU : MForm<0x0C, "ldwu $RA,$DISP($RB)">; //Load zero-extended word
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//Stores, float
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let OperandList = (ops F4RC:$RA, s16imm:$DISP, GPRC:$RB) in
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def STS : MFormAlt<0x26, "sts $RA,$DISP($RB)">; //Store S_floating
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let OperandList = (ops F8RC:$RA, s16imm:$DISP, GPRC:$RB) in
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def STT : MFormAlt<0x27, "stt $RA,$DISP($RB)">; //Store T_floating
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//Loads, float
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let OperandList = (ops F4RC:$RA, s16imm:$DISP, GPRC:$RB) in
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def LDS : MFormAlt<0x22, "lds $RA,$DISP($RB)">; //Load S_floating
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let OperandList = (ops F8RC:$RA, s16imm:$DISP, GPRC:$RB) in
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def LDT : MFormAlt<0x23, "ldt $RA,$DISP($RB)">; //Load T_floating
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}
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//Load address
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def LDA : MForm<0x08, "lda $RA,$DISP($RB)">; //Load address
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def LDAH : MForm<0x09, "ldah $RA,$DISP($RB)">; //Load address high
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let isLoad = 1 in {
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//Loads, int, Rellocated Low form
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def LDLr : MForm<0x28, "ldl $RA,$DISP($RB)\t\t!gprellow">; // Load sign-extended longword
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def LDQr : MForm<0x29, "ldq $RA,$DISP($RB)\t\t!gprellow">; //Load quadword
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@ -517,19 +530,22 @@ let OperandList = (ops F4RC:$RA, s16imm:$DISP, GPRC:$RB) in
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def LDSr : MFormAlt<0x22, "lds $RA,$DISP($RB)\t\t!gprellow">; //Load S_floating
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let OperandList = (ops F8RC:$RA, s16imm:$DISP, GPRC:$RB) in
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def LDTr : MFormAlt<0x23, "ldt $RA,$DISP($RB)\t\t!gprellow">; //Load T_floating
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}
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//Load address, rellocated low and high form
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def LDAr : MForm<0x08, "lda $RA,$DISP($RB)\t\t!gprellow">; //Load address
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def LDAHr : MForm<0x09, "ldah $RA,$DISP($RB)\t\t!gprelhigh">; //Load address high
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//load address, rellocated gpdist form
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def LDAg : MgForm<0x08, "lda $RA,0($RB)\t\t!gpdisp!$NUM">; //Load address
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def LDAHg : MgForm<0x09, "ldah $RA,0($RB)\t\t!gpdisp!$NUM">; //Load address
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//Load quad, rellocated literal form
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let isLoad = 1 in
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def LDQl : MForm<0x29, "ldq $RA,$DISP($RB)\t\t!literal">; //Load quadword
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let isStore = 1 in {
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//Stores, int
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def STBr : MForm<0x0E, "stb $RA,$DISP($RB)\t\t!gprellow">; // Store byte
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def STWr : MForm<0x0D, "stw $RA,$DISP($RB)\t\t!gprellow">; // Store word
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@ -541,7 +557,7 @@ let OperandList = (ops F4RC:$RA, s16imm:$DISP, GPRC:$RB) in
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def STSr : MFormAlt<0x26, "sts $RA,$DISP($RB)\t\t!gprellow">; //Store S_floating
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let OperandList = (ops F8RC:$RA, s16imm:$DISP, GPRC:$RB) in
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def STTr : MFormAlt<0x27, "stt $RA,$DISP($RB)\t\t!gprellow">; //Store T_floating
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}
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//Branches, int
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def BEQ : BForm<0x39, "beq $RA,$DISP">; //Branch if = zero
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@ -803,3 +819,42 @@ def : Pat<(fneg F4RC:$RB),
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def : Pat<(mulhs GPRC:$RA, GPRC:$RB),
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(SUBQ (UMULH GPRC:$RA, GPRC:$RB), (ADDQ (CMOVGE GPRC:$RB, R31, GPRC:$RA),
|
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(CMOVGE GPRC:$RA, R31, GPRC:$RB)))>;
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|
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def : Pat<(Alpha_gprello tglobaladdr:$in, GPRC:$reg),
|
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(LDAr tglobaladdr:$in, GPRC:$reg)>;
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def : Pat<(Alpha_gprelhi tglobaladdr:$in, GPRC:$reg),
|
||||
(LDAHr tglobaladdr:$in, GPRC:$reg)>;
|
||||
|
||||
//GOT Relative loads
|
||||
def : Pat<(i64 (load (Alpha_gprello tglobaladdr:$in, GPRC:$reg))),
|
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(LDQr tglobaladdr:$in, GPRC:$reg)>;
|
||||
def : Pat<(f64 (load (Alpha_gprello tglobaladdr:$in, GPRC:$reg))),
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(LDTr tglobaladdr:$in, GPRC:$reg)>;
|
||||
def : Pat<(f32 (load (Alpha_gprello tglobaladdr:$in, GPRC:$reg))),
|
||||
(LDSr tglobaladdr:$in, GPRC:$reg)>;
|
||||
def : Pat<(i64 (sextload (Alpha_gprello tglobaladdr:$in, GPRC:$reg), i32)),
|
||||
(LDLr tglobaladdr:$in, GPRC:$reg)>;
|
||||
def : Pat<(i64 (extload (Alpha_gprello tglobaladdr:$in, GPRC:$reg), i32)),
|
||||
(LDLr tglobaladdr:$in, GPRC:$reg)>;
|
||||
def : Pat<(i64 (zextload (Alpha_gprello tglobaladdr:$in, GPRC:$reg), i16)),
|
||||
(LDWUr tglobaladdr:$in, GPRC:$reg)>;
|
||||
def : Pat<(i64 (extload (Alpha_gprello tglobaladdr:$in, GPRC:$reg), i16)),
|
||||
(LDWUr tglobaladdr:$in, GPRC:$reg)>;
|
||||
def : Pat<(i64 (zextload (Alpha_gprello tglobaladdr:$in, GPRC:$reg), i8)),
|
||||
(LDBUr tglobaladdr:$in, GPRC:$reg)>;
|
||||
def : Pat<(i64 (extload (Alpha_gprello tglobaladdr:$in, GPRC:$reg), i8)),
|
||||
(LDBUr tglobaladdr:$in, GPRC:$reg)>;
|
||||
|
||||
//GOT Relative Stores
|
||||
def : Pat<(store GPRC:$val, (Alpha_gprello tglobaladdr:$in, GPRC:$reg)),
|
||||
(STQr GPRC:$val, tglobaladdr:$in, GPRC:$reg)>;
|
||||
def : Pat<(store F8RC:$val, (Alpha_gprello tglobaladdr:$in, GPRC:$reg)),
|
||||
(STTr F8RC:$val, tglobaladdr:$in, GPRC:$reg)>;
|
||||
def : Pat<(store F4RC:$val, (Alpha_gprello tglobaladdr:$in, GPRC:$reg)),
|
||||
(STSr F4RC:$val, tglobaladdr:$in, GPRC:$reg)>;
|
||||
def : Pat<(truncstore GPRC:$val, (Alpha_gprello tglobaladdr:$in, GPRC:$reg), i32),
|
||||
(STLr GPRC:$val, tglobaladdr:$in, GPRC:$reg)>;
|
||||
def : Pat<(truncstore GPRC:$val, (Alpha_gprello tglobaladdr:$in, GPRC:$reg), i16),
|
||||
(STWr GPRC:$val, tglobaladdr:$in, GPRC:$reg)>;
|
||||
def : Pat<(truncstore GPRC:$val, (Alpha_gprello tglobaladdr:$in, GPRC:$reg), i8),
|
||||
(STBr GPRC:$val, tglobaladdr:$in, GPRC:$reg)>;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user