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https://github.com/c64scene-ar/llvm-6502.git
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4e62951282
Lower GOT relative addresses to Lo and HI. Update both ISels to select them when they can. Saves instructions here and there. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25001 91177308-0d34-0410-b5e6-96231b3b80d8
469 lines
18 KiB
C++
469 lines
18 KiB
C++
//===-- AlphaISelLowering.cpp - Alpha DAG Lowering Implementation ---------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by Andrew Lenharth and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the AlphaISelLowering class.
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//
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//===----------------------------------------------------------------------===//
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#include "AlphaISelLowering.h"
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#include "AlphaTargetMachine.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/CodeGen/SSARegMap.h"
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#include "llvm/Constants.h"
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#include "llvm/Function.h"
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#include "llvm/Support/CommandLine.h"
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#include <iostream>
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using namespace llvm;
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namespace llvm {
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extern cl::opt<bool> EnableAlphaIDIV;
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extern cl::opt<bool> EnableAlphaCount;
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extern cl::opt<bool> EnableAlphaLSMark;
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}
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/// AddLiveIn - This helper function adds the specified physical register to the
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/// MachineFunction as a live in value. It also creates a corresponding virtual
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/// register for it.
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static unsigned AddLiveIn(MachineFunction &MF, unsigned PReg,
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TargetRegisterClass *RC) {
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assert(RC->contains(PReg) && "Not the correct regclass!");
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unsigned VReg = MF.getSSARegMap()->createVirtualRegister(RC);
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MF.addLiveIn(PReg, VReg);
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return VReg;
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}
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AlphaTargetLowering::AlphaTargetLowering(TargetMachine &TM) : TargetLowering(TM) {
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// Set up the TargetLowering object.
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//I am having problems with shr n ubyte 1
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setShiftAmountType(MVT::i64);
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setSetCCResultType(MVT::i64);
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setSetCCResultContents(ZeroOrOneSetCCResult);
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addRegisterClass(MVT::i64, Alpha::GPRCRegisterClass);
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addRegisterClass(MVT::f64, Alpha::F8RCRegisterClass);
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addRegisterClass(MVT::f32, Alpha::F4RCRegisterClass);
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setOperationAction(ISD::BRCONDTWOWAY, MVT::Other, Expand);
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setOperationAction(ISD::BRTWOWAY_CC, MVT::Other, Expand);
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setOperationAction(ISD::EXTLOAD, MVT::i1, Promote);
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setOperationAction(ISD::EXTLOAD, MVT::f32, Expand);
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setOperationAction(ISD::ZEXTLOAD, MVT::i1, Promote);
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setOperationAction(ISD::ZEXTLOAD, MVT::i32, Expand);
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setOperationAction(ISD::SEXTLOAD, MVT::i1, Promote);
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setOperationAction(ISD::SEXTLOAD, MVT::i8, Expand);
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setOperationAction(ISD::SEXTLOAD, MVT::i16, Expand);
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setOperationAction(ISD::TRUNCSTORE, MVT::i1, Promote);
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setOperationAction(ISD::FREM, MVT::f32, Expand);
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setOperationAction(ISD::FREM, MVT::f64, Expand);
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setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
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setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
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setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
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setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
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if (!TM.getSubtarget<AlphaSubtarget>().hasCT()) {
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setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
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setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
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setOperationAction(ISD::CTLZ , MVT::i64 , Expand);
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}
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//If this didn't legalize into a div....
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// setOperationAction(ISD::SREM , MVT::i64, Expand);
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// setOperationAction(ISD::UREM , MVT::i64, Expand);
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setOperationAction(ISD::MEMMOVE , MVT::Other, Expand);
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setOperationAction(ISD::MEMSET , MVT::Other, Expand);
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setOperationAction(ISD::MEMCPY , MVT::Other, Expand);
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// We don't support sin/cos/sqrt
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setOperationAction(ISD::FSIN , MVT::f64, Expand);
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setOperationAction(ISD::FCOS , MVT::f64, Expand);
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setOperationAction(ISD::FSQRT, MVT::f64, Expand);
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setOperationAction(ISD::FSIN , MVT::f32, Expand);
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setOperationAction(ISD::FCOS , MVT::f32, Expand);
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setOperationAction(ISD::FSQRT, MVT::f32, Expand);
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setOperationAction(ISD::SETCC, MVT::f32, Promote);
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// We don't have line number support yet.
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setOperationAction(ISD::LOCATION, MVT::Other, Expand);
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setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
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// We want to legalize GlobalAddress and ConstantPool nodes into the
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// appropriate instructions to materialize the address.
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setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
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setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
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addLegalFPImmediate(+0.0); //F31
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addLegalFPImmediate(-0.0); //-F31
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computeRegisterProperties();
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useITOF = TM.getSubtarget<AlphaSubtarget>().hasF2I();
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}
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//http://www.cs.arizona.edu/computer.help/policy/DIGITAL_unix/AA-PY8AC-TET1_html/callCH3.html#BLOCK21
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//For now, just use variable size stack frame format
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//In a standard call, the first six items are passed in registers $16
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//- $21 and/or registers $f16 - $f21. (See Section 4.1.2 for details
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//of argument-to-register correspondence.) The remaining items are
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//collected in a memory argument list that is a naturally aligned
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//array of quadwords. In a standard call, this list, if present, must
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//be passed at 0(SP).
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//7 ... n 0(SP) ... (n-7)*8(SP)
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// //#define FP $15
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// //#define RA $26
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// //#define PV $27
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// //#define GP $29
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// //#define SP $30
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std::vector<SDOperand>
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AlphaTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG)
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{
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MachineFunction &MF = DAG.getMachineFunction();
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MachineFrameInfo *MFI = MF.getFrameInfo();
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MachineBasicBlock& BB = MF.front();
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std::vector<SDOperand> ArgValues;
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unsigned args_int[] = {
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Alpha::R16, Alpha::R17, Alpha::R18, Alpha::R19, Alpha::R20, Alpha::R21};
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unsigned args_float[] = {
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Alpha::F16, Alpha::F17, Alpha::F18, Alpha::F19, Alpha::F20, Alpha::F21};
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int count = 0;
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GP = AddLiveIn(MF, Alpha::R29, getRegClassFor(MVT::i64));
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RA = AddLiveIn(MF, Alpha::R26, getRegClassFor(MVT::i64));
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for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I)
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{
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SDOperand argt;
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if (count < 6) {
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unsigned Vreg;
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MVT::ValueType VT = getValueType(I->getType());
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switch (VT) {
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default:
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std::cerr << "Unknown Type " << VT << "\n";
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abort();
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case MVT::f64:
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case MVT::f32:
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args_float[count] = AddLiveIn(MF, args_float[count], getRegClassFor(VT));
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argt = DAG.getCopyFromReg(DAG.getRoot(), args_float[count], VT);
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DAG.setRoot(argt.getValue(1));
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break;
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case MVT::i1:
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case MVT::i8:
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case MVT::i16:
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case MVT::i32:
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case MVT::i64:
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args_int[count] = AddLiveIn(MF, args_int[count], getRegClassFor(MVT::i64));
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argt = DAG.getCopyFromReg(DAG.getRoot(), args_int[count], MVT::i64);
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DAG.setRoot(argt.getValue(1));
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if (VT != MVT::i64) {
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unsigned AssertOp =
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I->getType()->isSigned() ? ISD::AssertSext : ISD::AssertZext;
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argt = DAG.getNode(AssertOp, MVT::i64, argt,
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DAG.getValueType(VT));
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argt = DAG.getNode(ISD::TRUNCATE, VT, argt);
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}
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break;
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}
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} else { //more args
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// Create the frame index object for this incoming parameter...
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int FI = MFI->CreateFixedObject(8, 8 * (count - 6));
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// Create the SelectionDAG nodes corresponding to a load
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//from this parameter
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SDOperand FIN = DAG.getFrameIndex(FI, MVT::i64);
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argt = DAG.getLoad(getValueType(I->getType()),
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DAG.getEntryNode(), FIN, DAG.getSrcValue(NULL));
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}
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++count;
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ArgValues.push_back(argt);
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}
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// If the functions takes variable number of arguments, copy all regs to stack
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if (F.isVarArg()) {
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VarArgsOffset = count * 8;
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std::vector<SDOperand> LS;
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for (int i = 0; i < 6; ++i) {
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if (MRegisterInfo::isPhysicalRegister(args_int[i]))
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args_int[i] = AddLiveIn(MF, args_int[i], getRegClassFor(MVT::i64));
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SDOperand argt = DAG.getCopyFromReg(DAG.getRoot(), args_int[i], MVT::i64);
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int FI = MFI->CreateFixedObject(8, -8 * (6 - i));
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if (i == 0) VarArgsBase = FI;
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SDOperand SDFI = DAG.getFrameIndex(FI, MVT::i64);
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LS.push_back(DAG.getNode(ISD::STORE, MVT::Other, DAG.getRoot(), argt,
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SDFI, DAG.getSrcValue(NULL)));
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if (MRegisterInfo::isPhysicalRegister(args_float[i]))
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args_float[i] = AddLiveIn(MF, args_float[i], getRegClassFor(MVT::f64));
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argt = DAG.getCopyFromReg(DAG.getRoot(), args_float[i], MVT::f64);
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FI = MFI->CreateFixedObject(8, - 8 * (12 - i));
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SDFI = DAG.getFrameIndex(FI, MVT::i64);
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LS.push_back(DAG.getNode(ISD::STORE, MVT::Other, DAG.getRoot(), argt,
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SDFI, DAG.getSrcValue(NULL)));
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}
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//Set up a token factor with all the stack traffic
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DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, LS));
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}
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// Finally, inform the code generator which regs we return values in.
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switch (getValueType(F.getReturnType())) {
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default: assert(0 && "Unknown type!");
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case MVT::isVoid: break;
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case MVT::i1:
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case MVT::i8:
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case MVT::i16:
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case MVT::i32:
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case MVT::i64:
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MF.addLiveOut(Alpha::R0);
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break;
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case MVT::f32:
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case MVT::f64:
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MF.addLiveOut(Alpha::F0);
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break;
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}
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//return the arguments
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return ArgValues;
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}
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std::pair<SDOperand, SDOperand>
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AlphaTargetLowering::LowerCallTo(SDOperand Chain,
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const Type *RetTy, bool isVarArg,
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unsigned CallingConv, bool isTailCall,
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SDOperand Callee, ArgListTy &Args,
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SelectionDAG &DAG) {
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int NumBytes = 0;
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if (Args.size() > 6)
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NumBytes = (Args.size() - 6) * 8;
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Chain = DAG.getNode(ISD::CALLSEQ_START, MVT::Other, Chain,
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DAG.getConstant(NumBytes, getPointerTy()));
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std::vector<SDOperand> args_to_use;
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for (unsigned i = 0, e = Args.size(); i != e; ++i)
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{
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switch (getValueType(Args[i].second)) {
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default: assert(0 && "Unexpected ValueType for argument!");
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case MVT::i1:
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case MVT::i8:
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case MVT::i16:
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case MVT::i32:
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// Promote the integer to 64 bits. If the input type is signed use a
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// sign extend, otherwise use a zero extend.
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if (Args[i].second->isSigned())
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Args[i].first = DAG.getNode(ISD::SIGN_EXTEND, MVT::i64, Args[i].first);
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else
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Args[i].first = DAG.getNode(ISD::ZERO_EXTEND, MVT::i64, Args[i].first);
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break;
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case MVT::i64:
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case MVT::f64:
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case MVT::f32:
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break;
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}
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args_to_use.push_back(Args[i].first);
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}
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std::vector<MVT::ValueType> RetVals;
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MVT::ValueType RetTyVT = getValueType(RetTy);
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MVT::ValueType ActualRetTyVT = RetTyVT;
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if (RetTyVT >= MVT::i1 && RetTyVT <= MVT::i32)
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ActualRetTyVT = MVT::i64;
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if (RetTyVT != MVT::isVoid)
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RetVals.push_back(ActualRetTyVT);
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RetVals.push_back(MVT::Other);
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SDOperand TheCall = SDOperand(DAG.getCall(RetVals,
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Chain, Callee, args_to_use), 0);
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Chain = TheCall.getValue(RetTyVT != MVT::isVoid);
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Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain,
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DAG.getConstant(NumBytes, getPointerTy()));
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SDOperand RetVal = TheCall;
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if (RetTyVT != ActualRetTyVT) {
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RetVal = DAG.getNode(RetTy->isSigned() ? ISD::AssertSext : ISD::AssertZext,
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MVT::i64, RetVal, DAG.getValueType(RetTyVT));
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RetVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, RetVal);
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}
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return std::make_pair(RetVal, Chain);
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}
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SDOperand AlphaTargetLowering::LowerVAStart(SDOperand Chain, SDOperand VAListP,
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Value *VAListV, SelectionDAG &DAG) {
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// vastart stores the address of the VarArgsBase and VarArgsOffset
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SDOperand FR = DAG.getFrameIndex(VarArgsBase, MVT::i64);
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SDOperand S1 = DAG.getNode(ISD::STORE, MVT::Other, Chain, FR, VAListP,
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DAG.getSrcValue(VAListV));
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SDOperand SA2 = DAG.getNode(ISD::ADD, MVT::i64, VAListP,
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DAG.getConstant(8, MVT::i64));
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return DAG.getNode(ISD::TRUNCSTORE, MVT::Other, S1,
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DAG.getConstant(VarArgsOffset, MVT::i64), SA2,
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DAG.getSrcValue(VAListV, 8), DAG.getValueType(MVT::i32));
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}
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std::pair<SDOperand,SDOperand> AlphaTargetLowering::
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LowerVAArg(SDOperand Chain, SDOperand VAListP, Value *VAListV,
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const Type *ArgTy, SelectionDAG &DAG) {
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SDOperand Base = DAG.getLoad(MVT::i64, Chain, VAListP,
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DAG.getSrcValue(VAListV));
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SDOperand Tmp = DAG.getNode(ISD::ADD, MVT::i64, VAListP,
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DAG.getConstant(8, MVT::i64));
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SDOperand Offset = DAG.getExtLoad(ISD::SEXTLOAD, MVT::i64, Base.getValue(1),
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Tmp, DAG.getSrcValue(VAListV, 8), MVT::i32);
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SDOperand DataPtr = DAG.getNode(ISD::ADD, MVT::i64, Base, Offset);
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if (ArgTy->isFloatingPoint())
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{
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//if fp && Offset < 6*8, then subtract 6*8 from DataPtr
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SDOperand FPDataPtr = DAG.getNode(ISD::SUB, MVT::i64, DataPtr,
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DAG.getConstant(8*6, MVT::i64));
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SDOperand CC = DAG.getSetCC(MVT::i64, Offset,
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DAG.getConstant(8*6, MVT::i64), ISD::SETLT);
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DataPtr = DAG.getNode(ISD::SELECT, MVT::i64, CC, FPDataPtr, DataPtr);
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}
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SDOperand Result;
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if (ArgTy == Type::IntTy)
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Result = DAG.getExtLoad(ISD::SEXTLOAD, MVT::i64, Offset.getValue(1),
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DataPtr, DAG.getSrcValue(NULL), MVT::i32);
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else if (ArgTy == Type::UIntTy)
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Result = DAG.getExtLoad(ISD::ZEXTLOAD, MVT::i64, Offset.getValue(1),
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DataPtr, DAG.getSrcValue(NULL), MVT::i32);
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else
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Result = DAG.getLoad(getValueType(ArgTy), Offset.getValue(1), DataPtr,
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DAG.getSrcValue(NULL));
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SDOperand NewOffset = DAG.getNode(ISD::ADD, MVT::i64, Offset,
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DAG.getConstant(8, MVT::i64));
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SDOperand Update = DAG.getNode(ISD::TRUNCSTORE, MVT::Other,
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Result.getValue(1), NewOffset,
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Tmp, DAG.getSrcValue(VAListV, 8),
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DAG.getValueType(MVT::i32));
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Result = DAG.getNode(ISD::TRUNCATE, getValueType(ArgTy), Result);
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return std::make_pair(Result, Update);
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}
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SDOperand AlphaTargetLowering::
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LowerVACopy(SDOperand Chain, SDOperand SrcP, Value *SrcV, SDOperand DestP,
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Value *DestV, SelectionDAG &DAG) {
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SDOperand Val = DAG.getLoad(getPointerTy(), Chain, SrcP,
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DAG.getSrcValue(SrcV));
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SDOperand Result = DAG.getNode(ISD::STORE, MVT::Other, Val.getValue(1),
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Val, DestP, DAG.getSrcValue(DestV));
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SDOperand NP = DAG.getNode(ISD::ADD, MVT::i64, SrcP,
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DAG.getConstant(8, MVT::i64));
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Val = DAG.getExtLoad(ISD::SEXTLOAD, MVT::i64, Result, NP,
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DAG.getSrcValue(SrcV, 8), MVT::i32);
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SDOperand NPD = DAG.getNode(ISD::ADD, MVT::i64, DestP,
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DAG.getConstant(8, MVT::i64));
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return DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Val.getValue(1),
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Val, NPD, DAG.getSrcValue(DestV, 8),
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DAG.getValueType(MVT::i32));
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}
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void AlphaTargetLowering::restoreGP(MachineBasicBlock* BB)
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{
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BuildMI(BB, Alpha::BIS, 2, Alpha::R29).addReg(GP).addReg(GP);
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}
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void AlphaTargetLowering::restoreRA(MachineBasicBlock* BB)
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{
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BuildMI(BB, Alpha::BIS, 2, Alpha::R26).addReg(RA).addReg(RA);
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}
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/// LowerOperation - Provide custom lowering hooks for some operations.
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///
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SDOperand AlphaTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
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switch (Op.getOpcode()) {
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default: assert(0 && "Wasn't expecting to be able to lower this!");
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case ISD::SINT_TO_FP: {
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assert(MVT::i64 == Op.getOperand(0).getValueType() &&
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"Unhandled SINT_TO_FP type in custom expander!");
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SDOperand LD;
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bool isDouble = MVT::f64 == Op.getValueType();
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if (useITOF) {
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LD = DAG.getNode(AlphaISD::ITOFT_, MVT::f64, Op.getOperand(0));
|
|
} else {
|
|
int FrameIdx =
|
|
DAG.getMachineFunction().getFrameInfo()->CreateStackObject(8, 8);
|
|
SDOperand FI = DAG.getFrameIndex(FrameIdx, MVT::i64);
|
|
SDOperand ST = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
|
|
Op.getOperand(0), FI, DAG.getSrcValue(0));
|
|
LD = DAG.getLoad(MVT::f64, ST, FI, DAG.getSrcValue(0));
|
|
}
|
|
SDOperand FP = DAG.getNode(isDouble?AlphaISD::CVTQT_:AlphaISD::CVTQS_,
|
|
isDouble?MVT::f64:MVT::f32, LD);
|
|
return FP;
|
|
}
|
|
case ISD::FP_TO_SINT: {
|
|
bool isDouble = MVT::f64 == Op.getOperand(0).getValueType();
|
|
SDOperand src = Op.getOperand(0);
|
|
|
|
if (!isDouble) //Promote
|
|
src = DAG.getNode(ISD::FP_EXTEND, MVT::f64, src);
|
|
|
|
src = DAG.getNode(AlphaISD::CVTTQ_, MVT::f64, src);
|
|
|
|
if (useITOF) {
|
|
return DAG.getNode(AlphaISD::FTOIT_, MVT::i64, src);
|
|
} else {
|
|
int FrameIdx =
|
|
DAG.getMachineFunction().getFrameInfo()->CreateStackObject(8, 8);
|
|
SDOperand FI = DAG.getFrameIndex(FrameIdx, MVT::i64);
|
|
SDOperand ST = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
|
|
src, FI, DAG.getSrcValue(0));
|
|
return DAG.getLoad(MVT::i64, ST, FI, DAG.getSrcValue(0));
|
|
}
|
|
}
|
|
case ISD::ConstantPool: {
|
|
Constant *C = cast<ConstantPoolSDNode>(Op)->get();
|
|
SDOperand CPI = DAG.getTargetConstantPool(C, MVT::i64);
|
|
|
|
SDOperand Hi = DAG.getNode(AlphaISD::GPRelHi, MVT::i64, CPI,
|
|
DAG.getNode(AlphaISD::GlobalBaseReg, MVT::i64));
|
|
SDOperand Lo = DAG.getNode(AlphaISD::GPRelLo, MVT::i64, CPI, Hi);
|
|
return Lo;
|
|
}
|
|
case ISD::GlobalAddress: {
|
|
GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
|
|
GlobalValue *GV = GSDN->getGlobal();
|
|
SDOperand GA = DAG.getTargetGlobalAddress(GV, MVT::i64, GSDN->getOffset());
|
|
|
|
if (!GV->hasWeakLinkage() && !GV->isExternal()) {
|
|
SDOperand Hi = DAG.getNode(AlphaISD::GPRelHi, MVT::i64, GA,
|
|
DAG.getNode(AlphaISD::GlobalBaseReg, MVT::i64));
|
|
SDOperand Lo = DAG.getNode(AlphaISD::GPRelLo, MVT::i64, GA, Hi);
|
|
return Lo;
|
|
} else
|
|
return GA;
|
|
}
|
|
|
|
}
|
|
|
|
return SDOperand();
|
|
}
|