mirror of
https://github.com/c64scene-ar/llvm-6502.git
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Implement first round of feedback from chris (there's still a couple things
left to do). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23195 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Nate Begeman
parent
2b8ad8e55a
commit
4ebd805c6a
@ -1,4 +1,4 @@
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//===-- DAGCombiner.cpp - Implement a trivial DAG combiner ----------------===//
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//===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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@ -21,10 +21,16 @@
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// we don't have yet.
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//
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// FIXME: mul (x, const) -> shifts + adds
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//
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// FIXME: undef values
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//
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// FIXME: zero extend when top bits are 0 -> drop it ?
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// FIXME: make truncate see through SIGN_EXTEND and AND
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// FIXME: sext_in_reg(setcc) on targets that return zero or one, and where
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// EVT != MVT::i1 can drop the sext.
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// FIXME: (or x, c) -> c iff maskedValueIsZero(x, ~c)
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// FIXME: MaskedValueIsZero can see through SRL, so it should be sufficient to:
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//if (N2C && MaskedValueIsZero(SDOperand(N, 0), ~0ULL >> (64-OpSizeInBits),TLI))
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// return DAG.getConstant(0, VT).Val;
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// FIXME: (sra (sra x, c1), c2) -> (sra x, c1+c2)
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//
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//===----------------------------------------------------------------------===//
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@ -42,6 +48,7 @@ namespace {
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class DAGCombiner {
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SelectionDAG &DAG;
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TargetLowering &TLI;
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bool AfterLegalize;
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// Worklist of all of the nodes that need to be simplified.
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std::vector<SDNode*> WorkList;
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@ -52,11 +59,8 @@ namespace {
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///
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void AddUsersToWorkList(SDNode *N) {
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for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
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UI != UE; ++UI) {
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SDNode *U = *UI;
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for (unsigned i = 0, e = U->getNumOperands(); i != e; ++i)
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WorkList.push_back(U->getOperand(i).Val);
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}
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UI != UE; ++UI)
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WorkList.push_back(*UI);
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}
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/// removeFromWorkList - remove all instances of N from the worklist.
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@ -120,13 +124,13 @@ namespace {
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// brtwoway_cc
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public:
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DAGCombiner(SelectionDAG &D)
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: DAG(D), TLI(D.getTargetLoweringInfo()) {
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: DAG(D), TLI(D.getTargetLoweringInfo()), AfterLegalize(false) {
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// Add all the dag nodes to the worklist.
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WorkList.insert(WorkList.end(), D.allnodes_begin(), D.allnodes_end());
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}
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/// Run - runs the dag combiner on all nodes in the work list
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void Run(bool AfterLegalize);
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void Run(bool RunningAfterLegalize);
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};
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}
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@ -140,79 +144,69 @@ static bool MaskedValueIsZero(const SDOperand &Op, uint64_t Mask,
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// If we know the result of a setcc has the top bits zero, use this info.
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switch (Op.getOpcode()) {
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case ISD::Constant:
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return (cast<ConstantSDNode>(Op)->getValue() & Mask) == 0;
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case ISD::SETCC:
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return ((Mask & 1) == 0) &&
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TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult;
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case ISD::ZEXTLOAD:
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SrcBits = MVT::getSizeInBits(cast<VTSDNode>(Op.getOperand(3))->getVT());
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return (Mask & ((1ULL << SrcBits)-1)) == 0; // Returning only the zext bits.
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case ISD::ZERO_EXTEND:
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case ISD::AssertZext:
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SrcBits = MVT::getSizeInBits(Op.getOperand(0).getValueType());
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return MaskedValueIsZero(Op.getOperand(0),Mask & ((1ULL << SrcBits)-1),TLI);
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case ISD::AND:
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// (X & C1) & C2 == 0 iff C1 & C2 == 0.
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if (ConstantSDNode *AndRHS = dyn_cast<ConstantSDNode>(Op.getOperand(1)))
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return MaskedValueIsZero(Op.getOperand(0),AndRHS->getValue() & Mask, TLI);
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// FALL THROUGH
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case ISD::OR:
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case ISD::XOR:
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return MaskedValueIsZero(Op.getOperand(0), Mask, TLI) &&
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MaskedValueIsZero(Op.getOperand(1), Mask, TLI);
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case ISD::SELECT:
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return MaskedValueIsZero(Op.getOperand(1), Mask, TLI) &&
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MaskedValueIsZero(Op.getOperand(2), Mask, TLI);
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case ISD::SELECT_CC:
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return MaskedValueIsZero(Op.getOperand(2), Mask, TLI) &&
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MaskedValueIsZero(Op.getOperand(3), Mask, TLI);
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case ISD::SRL:
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// (ushr X, C1) & C2 == 0 iff X & (C2 << C1) == 0
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if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
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uint64_t NewVal = Mask << ShAmt->getValue();
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SrcBits = MVT::getSizeInBits(Op.getValueType());
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if (SrcBits != 64) NewVal &= (1ULL << SrcBits)-1;
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return MaskedValueIsZero(Op.getOperand(0), NewVal, TLI);
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}
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return false;
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case ISD::SHL:
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// (ushl X, C1) & C2 == 0 iff X & (C2 >> C1) == 0
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if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
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uint64_t NewVal = Mask >> ShAmt->getValue();
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return MaskedValueIsZero(Op.getOperand(0), NewVal, TLI);
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}
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return false;
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case ISD::CTTZ:
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case ISD::CTLZ:
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case ISD::CTPOP:
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// Bit counting instructions can not set the high bits of the result
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// register. The max number of bits sets depends on the input.
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return (Mask & (MVT::getSizeInBits(Op.getValueType())*2-1)) == 0;
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// TODO we could handle some SRA cases here.
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default: break;
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case ISD::Constant:
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return (cast<ConstantSDNode>(Op)->getValue() & Mask) == 0;
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case ISD::SETCC:
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return ((Mask & 1) == 0) &&
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TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult;
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case ISD::ZEXTLOAD:
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SrcBits = MVT::getSizeInBits(cast<VTSDNode>(Op.getOperand(3))->getVT());
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return (Mask & ((1ULL << SrcBits)-1)) == 0; // Returning only the zext bits.
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case ISD::ZERO_EXTEND:
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SrcBits = MVT::getSizeInBits(Op.getOperand(0).getValueType());
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return MaskedValueIsZero(Op.getOperand(0),Mask & ((1ULL << SrcBits)-1),TLI);
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case ISD::AssertZext:
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SrcBits = MVT::getSizeInBits(cast<VTSDNode>(Op.getOperand(1))->getVT());
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return (Mask & ((1ULL << SrcBits)-1)) == 0; // Returning only the zext bits.
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case ISD::AND:
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// (X & C1) & C2 == 0 iff C1 & C2 == 0.
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if (ConstantSDNode *AndRHS = dyn_cast<ConstantSDNode>(Op.getOperand(1)))
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return MaskedValueIsZero(Op.getOperand(0),AndRHS->getValue() & Mask, TLI);
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// FALL THROUGH
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case ISD::OR:
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case ISD::XOR:
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return MaskedValueIsZero(Op.getOperand(0), Mask, TLI) &&
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MaskedValueIsZero(Op.getOperand(1), Mask, TLI);
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case ISD::SELECT:
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return MaskedValueIsZero(Op.getOperand(1), Mask, TLI) &&
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MaskedValueIsZero(Op.getOperand(2), Mask, TLI);
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case ISD::SELECT_CC:
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return MaskedValueIsZero(Op.getOperand(2), Mask, TLI) &&
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MaskedValueIsZero(Op.getOperand(3), Mask, TLI);
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case ISD::SRL:
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// (ushr X, C1) & C2 == 0 iff X & (C2 << C1) == 0
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if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
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uint64_t NewVal = Mask << ShAmt->getValue();
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SrcBits = MVT::getSizeInBits(Op.getValueType());
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if (SrcBits != 64) NewVal &= (1ULL << SrcBits)-1;
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return MaskedValueIsZero(Op.getOperand(0), NewVal, TLI);
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}
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return false;
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case ISD::SHL:
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// (ushl X, C1) & C2 == 0 iff X & (C2 >> C1) == 0
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if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
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uint64_t NewVal = Mask >> ShAmt->getValue();
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return MaskedValueIsZero(Op.getOperand(0), NewVal, TLI);
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}
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return false;
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case ISD::CTTZ:
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case ISD::CTLZ:
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case ISD::CTPOP:
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// Bit counting instructions can not set the high bits of the result
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// register. The max number of bits sets depends on the input.
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return (Mask & (MVT::getSizeInBits(Op.getValueType())*2-1)) == 0;
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// TODO we could handle some SRA cases here.
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default: break;
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}
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return false;
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}
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// isInvertibleForFree - Return true if there is no cost to emitting the logical
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// inverse of this node.
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static bool isInvertibleForFree(SDOperand N) {
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if (isa<ConstantSDNode>(N.Val)) return true;
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if (N.Val->getOpcode() == ISD::SETCC && N.Val->hasOneUse())
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return true;
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return false;
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}
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// isSetCCEquivalent - Return true if this node is a select_cc that selects
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// between the values 1 and 0, making it equivalent to a setcc.
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// isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc
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// that selects between the values 1 and 0, making it equivalent to a setcc.
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static bool isSetCCEquivalent(SDOperand N) {
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if (N.getOpcode() == ISD::SETCC)
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return true;
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if (N.getOpcode() == ISD::SELECT_CC &&
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N.getOperand(2).getOpcode() == ISD::Constant &&
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N.getOperand(3).getOpcode() == ISD::Constant &&
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@ -222,7 +216,19 @@ static bool isSetCCEquivalent(SDOperand N) {
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return false;
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}
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void DAGCombiner::Run(bool AfterLegalize) {
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// isInvertibleForFree - Return true if there is no cost to emitting the logical
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// inverse of this node.
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static bool isInvertibleForFree(SDOperand N) {
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if (isa<ConstantSDNode>(N.Val)) return true;
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if (isSetCCEquivalent(N) && N.Val->hasOneUse())
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return true;
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return false;
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}
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void DAGCombiner::Run(bool RunningAfterLegalize) {
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// set the instance variable, so that the various visit routines may use it.
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AfterLegalize = RunningAfterLegalize;
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// while the worklist isn't empty, inspect the node on the end of it and
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// try and combine it.
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while (!WorkList.empty()) {
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@ -295,10 +301,6 @@ SDNode *DAGCombiner::visit(SDNode *N) {
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case ISD::FP_EXTEND: return visitFPExtend(N);
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case ISD::FNEG: return visitFneg(N);
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case ISD::FABS: return visitFabs(N);
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case ISD::EXTLOAD: return visitExtLoad(N);
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case ISD::SEXTLOAD: return visitSextLoad(N);
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case ISD::ZEXTLOAD: return visitZextLoad(N);
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case ISD::TRUNCSTORE: return visitTruncStore(N);
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}
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return 0;
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}
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@ -322,10 +324,10 @@ SDNode *DAGCombiner::visitTokenFactor(SDNode *N) {
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SDNode *DAGCombiner::visitAdd(SDNode *N) {
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SDOperand N0 = N->getOperand(0);
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SDOperand N1 = N->getOperand(1);
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ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N0.Val);
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ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N1.Val);
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ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N0.Val);
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ConstantFPSDNode *N2CFP = dyn_cast<ConstantFPSDNode>(N1.Val);
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ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N0);
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ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N1);
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ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N0);
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ConstantFPSDNode *N2CFP = dyn_cast<ConstantFPSDNode>(N1);
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// fold (add c1, c2) -> c1+c2
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if (N1C && N2C)
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@ -395,10 +397,10 @@ SDNode *DAGCombiner::visitSub(SDNode *N) {
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SDNode *DAGCombiner::visitMul(SDNode *N) {
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SDOperand N0 = N->getOperand(0);
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SDOperand N1 = N->getOperand(1);
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ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N0.Val);
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ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N1.Val);
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ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N0.Val);
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ConstantFPSDNode *N2CFP = dyn_cast<ConstantFPSDNode>(N1.Val);
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ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N0);
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ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N1);
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ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N0);
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ConstantFPSDNode *N2CFP = dyn_cast<ConstantFPSDNode>(N1);
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// fold (mul c1, c2) -> c1*c2
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if (N1C && N2C)
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@ -463,10 +465,10 @@ SDNode *DAGCombiner::visitUdiv(SDNode *N) {
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SDNode *DAGCombiner::visitSrem(SDNode *N) {
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SDOperand N0 = N->getOperand(0);
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SDOperand N1 = N->getOperand(1);
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ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N0.Val);
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ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N1.Val);
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ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N0.Val);
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ConstantFPSDNode *N2CFP = dyn_cast<ConstantFPSDNode>(N1.Val);
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ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N0);
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ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N1);
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ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N0);
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ConstantFPSDNode *N2CFP = dyn_cast<ConstantFPSDNode>(N1);
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// fold (srem c1, c2) -> c1%c2
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if (N1C && N2C)
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@ -482,8 +484,8 @@ SDNode *DAGCombiner::visitSrem(SDNode *N) {
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SDNode *DAGCombiner::visitUrem(SDNode *N) {
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SDOperand N0 = N->getOperand(0);
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SDOperand N1 = N->getOperand(1);
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ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N0.Val);
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ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N1.Val);
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ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N0);
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ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N1);
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// fold (urem c1, c2) -> c1%c2
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if (N1C && N2C)
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@ -495,7 +497,7 @@ SDNode *DAGCombiner::visitUrem(SDNode *N) {
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SDNode *DAGCombiner::visitMulHiS(SDNode *N) {
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SDOperand N0 = N->getOperand(0);
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SDOperand N1 = N->getOperand(1);
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ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N1.Val);
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ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N1);
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// fold (mulhs x, 0) -> 0
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if (N2C && N2C->isNullValue())
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@ -512,7 +514,7 @@ SDNode *DAGCombiner::visitMulHiS(SDNode *N) {
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SDNode *DAGCombiner::visitMulHiU(SDNode *N) {
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SDOperand N0 = N->getOperand(0);
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SDOperand N1 = N->getOperand(1);
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ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N1.Val);
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ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N1);
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// fold (mulhu x, 0) -> 0
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if (N2C && N2C->isNullValue())
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@ -527,27 +529,26 @@ SDNode *DAGCombiner::visitMulHiU(SDNode *N) {
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SDNode *DAGCombiner::visitAnd(SDNode *N) {
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SDOperand N0 = N->getOperand(0);
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SDOperand N1 = N->getOperand(1);
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ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N0.Val);
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ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N1.Val);
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ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N0);
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ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N1);
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MVT::ValueType VT = N1.getValueType();
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// fold (and c1, c2) -> c1&c2
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if (N1C && N2C)
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return DAG.getConstant(N1C->getValue() & N2C->getValue(), VT).Val;
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// fold (and x, 0) -> 0
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if (N2C && N2C->isNullValue())
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return N1.Val;
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// fold (and x, -1) -> x
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if (N2C && N2C->isAllOnesValue())
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return N0.Val;
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// fold (and x, 0) -> 0
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if (MaskedValueIsZero(N0, N2C->getValue(), TLI))
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if (N2C && MaskedValueIsZero(N0, N2C->getValue(), TLI))
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return DAG.getConstant(0, VT).Val;
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// fold (and x, mask containing x) -> x
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uint64_t NotC2 = ~N2C->getValue();
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if (MVT::i64 != VT) NotC2 &= (1ULL << MVT::getSizeInBits(VT))-1;
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if (MaskedValueIsZero(N0, NotC2, TLI))
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return N0.Val;
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if (N2C) {
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uint64_t NotC2 = ~N2C->getValue();
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NotC2 &= ~0ULL >> (64-MVT::getSizeInBits(VT));
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if (MaskedValueIsZero(N0, NotC2, TLI))
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return N0.Val;
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}
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// fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1)
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if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG) {
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unsigned ExtendBits =
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@ -560,21 +561,14 @@ SDNode *DAGCombiner::visitAnd(SDNode *N) {
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if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
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if ((ORI->getValue() & N2C->getValue()) == N2C->getValue())
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return N1.Val;
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// fold (and (assert_zext x, i16), 0xFFFF) -> (assert_zext x, i16)
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if (N0.getOpcode() == ISD::AssertZext) {
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unsigned ExtendBits =
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MVT::getSizeInBits(cast<VTSDNode>(N0.getOperand(1))->getVT());
|
||||
if (N2C->getValue() == (1ULL << ExtendBits)-1)
|
||||
return N0.Val;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
SDNode *DAGCombiner::visitOr(SDNode *N) {
|
||||
SDOperand N0 = N->getOperand(0);
|
||||
SDOperand N1 = N->getOperand(1);
|
||||
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N0.Val);
|
||||
ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N1.Val);
|
||||
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N0);
|
||||
ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N1);
|
||||
|
||||
// fold (or c1, c2) -> c1|c2
|
||||
if (N1C && N2C)
|
||||
@ -592,8 +586,8 @@ SDNode *DAGCombiner::visitOr(SDNode *N) {
|
||||
SDNode *DAGCombiner::visitXor(SDNode *N) {
|
||||
SDOperand N0 = N->getOperand(0);
|
||||
SDOperand N1 = N->getOperand(1);
|
||||
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N0.Val);
|
||||
ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N1.Val);
|
||||
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N0);
|
||||
ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N1);
|
||||
MVT::ValueType VT = N0.getValueType();
|
||||
|
||||
// fold (xor c1, c2) -> c1^c2
|
||||
@ -603,14 +597,14 @@ SDNode *DAGCombiner::visitXor(SDNode *N) {
|
||||
if (N2C && N2C->isNullValue())
|
||||
return N0.Val;
|
||||
// fold !(x cc y) -> (x !cc y)
|
||||
if (N2C && N2C->isAllOnesValue() && N0.getOpcode() == ISD::SETCC) {
|
||||
if (N2C && N2C->getValue() == 1 && N0.getOpcode() == ISD::SETCC) {
|
||||
bool isInt = MVT::isInteger(N0.getOperand(0).getValueType());
|
||||
ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get();
|
||||
return DAG.getSetCC(VT, N0.getOperand(0), N0.getOperand(1),
|
||||
ISD::getSetCCInverse(CC, isInt)).Val;
|
||||
}
|
||||
// fold !(x cc y) -> (x !cc y)
|
||||
if (N2C && N2C->isAllOnesValue() && isSetCCEquivalent(N0)) {
|
||||
if (N2C && N2C->getValue() == 1 && isSetCCEquivalent(N0)) {
|
||||
bool isInt = MVT::isInteger(N0.getOperand(0).getValueType());
|
||||
ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(4))->get();
|
||||
return DAG.getSelectCC(N0.getOperand(0), N0.getOperand(1),
|
||||
@ -641,8 +635,8 @@ SDNode *DAGCombiner::visitXor(SDNode *N) {
|
||||
SDNode *DAGCombiner::visitShl(SDNode *N) {
|
||||
SDOperand N0 = N->getOperand(0);
|
||||
SDOperand N1 = N->getOperand(1);
|
||||
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N0.Val);
|
||||
ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N1.Val);
|
||||
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N0);
|
||||
ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N1);
|
||||
MVT::ValueType VT = N0.getValueType();
|
||||
unsigned OpSizeInBits = MVT::getSizeInBits(VT);
|
||||
|
||||
@ -688,22 +682,17 @@ SDNode *DAGCombiner::visitShl(SDNode *N) {
|
||||
DAG.getConstant(c1-c2, N1.getValueType())).Val;
|
||||
}
|
||||
// fold (shl (sra x, c1), c1) -> (and x, -1 << c1)
|
||||
if (N2C && N0.getOpcode() == ISD::SRA &&
|
||||
N0.getOperand(1).getOpcode() == ISD::Constant) {
|
||||
uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
|
||||
uint64_t c2 = N2C->getValue();
|
||||
if (c1 == c2)
|
||||
return DAG.getNode(ISD::AND, VT, N0.getOperand(0),
|
||||
DAG.getConstant(~0ULL << c1, VT)).Val;
|
||||
}
|
||||
if (N2C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1))
|
||||
return DAG.getNode(ISD::AND, VT, N0.getOperand(0),
|
||||
DAG.getConstant(~0ULL << N2C->getValue(), VT)).Val;
|
||||
return 0;
|
||||
}
|
||||
|
||||
SDNode *DAGCombiner::visitSra(SDNode *N) {
|
||||
SDOperand N0 = N->getOperand(0);
|
||||
SDOperand N1 = N->getOperand(1);
|
||||
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N0.Val);
|
||||
ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N1.Val);
|
||||
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N0);
|
||||
ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N1);
|
||||
MVT::ValueType VT = N0.getValueType();
|
||||
unsigned OpSizeInBits = MVT::getSizeInBits(VT);
|
||||
|
||||
@ -731,8 +720,8 @@ SDNode *DAGCombiner::visitSra(SDNode *N) {
|
||||
SDNode *DAGCombiner::visitSrl(SDNode *N) {
|
||||
SDOperand N0 = N->getOperand(0);
|
||||
SDOperand N1 = N->getOperand(1);
|
||||
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N0.Val);
|
||||
ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N1.Val);
|
||||
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N0);
|
||||
ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N1);
|
||||
MVT::ValueType VT = N0.getValueType();
|
||||
unsigned OpSizeInBits = MVT::getSizeInBits(VT);
|
||||
|
||||
@ -767,7 +756,7 @@ SDNode *DAGCombiner::visitSrl(SDNode *N) {
|
||||
|
||||
SDNode *DAGCombiner::visitCtlz(SDNode *N) {
|
||||
SDOperand N0 = N->getOperand(0);
|
||||
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N0.Val);
|
||||
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N0);
|
||||
|
||||
// fold (ctlz c1) -> c2
|
||||
if (N1C)
|
||||
@ -778,7 +767,7 @@ SDNode *DAGCombiner::visitCtlz(SDNode *N) {
|
||||
|
||||
SDNode *DAGCombiner::visitCttz(SDNode *N) {
|
||||
SDOperand N0 = N->getOperand(0);
|
||||
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N0.Val);
|
||||
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N0);
|
||||
|
||||
// fold (cttz c1) -> c2
|
||||
if (N1C)
|
||||
@ -789,7 +778,7 @@ SDNode *DAGCombiner::visitCttz(SDNode *N) {
|
||||
|
||||
SDNode *DAGCombiner::visitCtpop(SDNode *N) {
|
||||
SDOperand N0 = N->getOperand(0);
|
||||
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N0.Val);
|
||||
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N0);
|
||||
|
||||
// fold (ctpop c1) -> c2
|
||||
if (N1C)
|
||||
@ -800,12 +789,9 @@ SDNode *DAGCombiner::visitCtpop(SDNode *N) {
|
||||
|
||||
SDNode *DAGCombiner::visitSignExtend(SDNode *N) {
|
||||
SDOperand N0 = N->getOperand(0);
|
||||
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N0.Val);
|
||||
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N0);
|
||||
MVT::ValueType VT = N->getValueType(0);
|
||||
|
||||
// noop sext
|
||||
if (N0.getValueType() == N->getValueType(0))
|
||||
return N0.Val;
|
||||
// fold (sext c1) -> c1
|
||||
if (N1C)
|
||||
return DAG.getConstant(N1C->getSignExtended(), VT).Val;
|
||||
@ -817,12 +803,9 @@ SDNode *DAGCombiner::visitSignExtend(SDNode *N) {
|
||||
|
||||
SDNode *DAGCombiner::visitZeroExtend(SDNode *N) {
|
||||
SDOperand N0 = N->getOperand(0);
|
||||
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N0.Val);
|
||||
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N0);
|
||||
MVT::ValueType VT = N->getValueType(0);
|
||||
|
||||
// noop zext
|
||||
if (N0.getValueType() == N->getValueType(0))
|
||||
return N0.Val;
|
||||
// fold (zext c1) -> c1
|
||||
if (N1C)
|
||||
return DAG.getConstant(N1C->getValue(), VT).Val;
|
||||
@ -834,13 +817,10 @@ SDNode *DAGCombiner::visitZeroExtend(SDNode *N) {
|
||||
|
||||
SDNode *DAGCombiner::visitSignExtendInReg(SDNode *N) {
|
||||
SDOperand N0 = N->getOperand(0);
|
||||
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N0.Val);
|
||||
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N0);
|
||||
MVT::ValueType VT = N->getValueType(0);
|
||||
MVT::ValueType EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
|
||||
|
||||
// noop sext_in_reg
|
||||
if (EVT == VT)
|
||||
return N0.Val;
|
||||
// fold (sext_in_reg c1) -> c1
|
||||
if (N1C) {
|
||||
SDOperand Truncate = DAG.getConstant(N1C->getValue(), EVT);
|
||||
@ -861,7 +841,7 @@ SDNode *DAGCombiner::visitSignExtendInReg(SDNode *N) {
|
||||
cast<VTSDNode>(N0.getOperand(3))->getVT() <= EVT) {
|
||||
return N0.Val;
|
||||
}
|
||||
// fold (sext_in_reg (setcc x)) -> setcc x iff (setcc x) == 0 or 1
|
||||
// fold (sext_in_reg (setcc x)) -> setcc x iff (setcc x) == 0 or -1
|
||||
if (N0.getOpcode() == ISD::SETCC &&
|
||||
TLI.getSetCCResultContents() ==
|
||||
TargetLowering::ZeroOrNegativeOneSetCCResult)
|
||||
@ -884,7 +864,7 @@ SDNode *DAGCombiner::visitSignExtendInReg(SDNode *N) {
|
||||
|
||||
SDNode *DAGCombiner::visitTruncate(SDNode *N) {
|
||||
SDOperand N0 = N->getOperand(0);
|
||||
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N0.Val);
|
||||
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N0);
|
||||
MVT::ValueType VT = N->getValueType(0);
|
||||
|
||||
// noop truncate
|
||||
@ -914,7 +894,7 @@ SDNode *DAGCombiner::visitTruncate(SDNode *N) {
|
||||
|
||||
SDNode *DAGCombiner::visitSintToFP(SDNode *N) {
|
||||
SDOperand N0 = N->getOperand(0);
|
||||
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N0.Val);
|
||||
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N0);
|
||||
MVT::ValueType VT = N->getValueType(0);
|
||||
|
||||
// fold (sint_to_fp c1) -> c1fp
|
||||
@ -925,7 +905,7 @@ SDNode *DAGCombiner::visitSintToFP(SDNode *N) {
|
||||
|
||||
SDNode *DAGCombiner::visitUintToFP(SDNode *N) {
|
||||
SDOperand N0 = N->getOperand(0);
|
||||
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N0.Val);
|
||||
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N0);
|
||||
MVT::ValueType VT = N->getValueType(0);
|
||||
|
||||
// fold (uint_to_fp c1) -> c1fp
|
||||
@ -1017,54 +997,10 @@ SDNode *DAGCombiner::visitFabs(SDNode *N) {
|
||||
return 0;
|
||||
}
|
||||
|
||||
SDNode *DAGCombiner::visitExtLoad(SDNode *N) {
|
||||
MVT::ValueType VT = N->getValueType(0);
|
||||
MVT::ValueType EVT = cast<VTSDNode>(N->getOperand(3))->getVT();
|
||||
|
||||
// fold (extload vt, x) -> (load x)
|
||||
if (EVT == VT)
|
||||
return DAG.getLoad(VT, N->getOperand(0), N->getOperand(1),
|
||||
N->getOperand(2)).Val;
|
||||
return 0;
|
||||
}
|
||||
|
||||
SDNode *DAGCombiner::visitSextLoad(SDNode *N) {
|
||||
MVT::ValueType VT = N->getValueType(0);
|
||||
MVT::ValueType EVT = cast<VTSDNode>(N->getOperand(3))->getVT();
|
||||
|
||||
// fold (sextload vt, x) -> (load x)
|
||||
if (EVT == VT)
|
||||
return DAG.getLoad(VT, N->getOperand(0), N->getOperand(1),
|
||||
N->getOperand(2)).Val;
|
||||
return 0;
|
||||
}
|
||||
|
||||
SDNode *DAGCombiner::visitZextLoad(SDNode *N) {
|
||||
MVT::ValueType VT = N->getValueType(0);
|
||||
MVT::ValueType EVT = cast<VTSDNode>(N->getOperand(3))->getVT();
|
||||
|
||||
// fold (zextload vt, x) -> (load x)
|
||||
if (EVT == VT)
|
||||
return DAG.getLoad(VT, N->getOperand(0), N->getOperand(1),
|
||||
N->getOperand(2)).Val;
|
||||
return 0;
|
||||
}
|
||||
|
||||
SDNode *DAGCombiner::visitTruncStore(SDNode *N) {
|
||||
MVT::ValueType VT = N->getValueType(0);
|
||||
MVT::ValueType EVT = cast<VTSDNode>(N->getOperand(4))->getVT();
|
||||
|
||||
// fold (truncstore x, vt) -> (store x)
|
||||
if (N->getOperand(0).getValueType() == EVT)
|
||||
return DAG.getNode(ISD::STORE, VT, N->getOperand(0), N->getOperand(1),
|
||||
N->getOperand(2), N->getOperand(3)).Val;
|
||||
return 0;
|
||||
}
|
||||
|
||||
// SelectionDAG::Combine - This is the entry point for the file.
|
||||
//
|
||||
void SelectionDAG::Combine(bool AfterLegalize) {
|
||||
void SelectionDAG::Combine(bool RunningAfterLegalize) {
|
||||
/// run - This is the main entry point to this class.
|
||||
///
|
||||
DAGCombiner(*this).Run(AfterLegalize);
|
||||
DAGCombiner(*this).Run(RunningAfterLegalize);
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user