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1007 lines
37 KiB
C++
1007 lines
37 KiB
C++
//===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by Nate Begeman and is distributed under the
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// University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run
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// both before and after the DAG is legalized.
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//
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// FIXME: Missing folds
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// sdiv, udiv, srem, urem (X, const) where X is an integer can be expanded into
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// a sequence of multiplies, shifts, and adds. This should be controlled by
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// some kind of hint from the target that int div is expensive.
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// various folds of mulh[s,u] by constants such as -1, powers of 2, etc.
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//
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// FIXME: Should add a corresponding version of fold AND with
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// ZERO_EXTEND/SIGN_EXTEND by converting them to an ANY_EXTEND node which
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// we don't have yet.
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//
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// FIXME: mul (x, const) -> shifts + adds
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// FIXME: undef values
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// FIXME: zero extend when top bits are 0 -> drop it ?
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// FIXME: make truncate see through SIGN_EXTEND and AND
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// FIXME: sext_in_reg(setcc) on targets that return zero or one, and where
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// EVT != MVT::i1 can drop the sext.
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// FIXME: (or x, c) -> c iff maskedValueIsZero(x, ~c)
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// FIXME: MaskedValueIsZero can see through SRL, so it should be sufficient to:
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//if (N2C && MaskedValueIsZero(SDOperand(N, 0), ~0ULL >> (64-OpSizeInBits),TLI))
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// return DAG.getConstant(0, VT).Val;
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// FIXME: (sra (sra x, c1), c2) -> (sra x, c1+c2)
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "dagcombine"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/Support/MathExtras.h"
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#include "llvm/Target/TargetLowering.h"
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#include <cmath>
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using namespace llvm;
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namespace {
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Statistic<> NodesCombined ("dagcombiner", "Number of dag nodes combined");
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class DAGCombiner {
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SelectionDAG &DAG;
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TargetLowering &TLI;
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bool AfterLegalize;
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// Worklist of all of the nodes that need to be simplified.
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std::vector<SDNode*> WorkList;
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/// AddUsersToWorkList - When an instruction is simplified, add all users of
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/// the instruction to the work lists because they might get more simplified
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/// now.
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///
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void AddUsersToWorkList(SDNode *N) {
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for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
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UI != UE; ++UI)
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WorkList.push_back(*UI);
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}
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/// removeFromWorkList - remove all instances of N from the worklist.
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void removeFromWorkList(SDNode *N) {
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WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N),
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WorkList.end());
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}
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/// visit - call the node-specific routine that knows how to fold each
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/// particular type of node.
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SDNode *visit(SDNode *N);
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// Visitation implementation - Implement dag node combining for different
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// node types. The semantics are as follows:
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// Return Value:
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// null - No change was made
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// otherwise - Node N should be replaced by the returned node.
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//
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SDNode *visitTokenFactor(SDNode *N);
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SDNode *visitAdd(SDNode *N);
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SDNode *visitSub(SDNode *N);
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SDNode *visitMul(SDNode *N);
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SDNode *visitSdiv(SDNode *N);
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SDNode *visitUdiv(SDNode *N);
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SDNode *visitSrem(SDNode *N);
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SDNode *visitUrem(SDNode *N);
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SDNode *visitMulHiU(SDNode *N);
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SDNode *visitMulHiS(SDNode *N);
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SDNode *visitAnd(SDNode *N);
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SDNode *visitOr(SDNode *N);
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SDNode *visitXor(SDNode *N);
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SDNode *visitShl(SDNode *N);
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SDNode *visitSra(SDNode *N);
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SDNode *visitSrl(SDNode *N);
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SDNode *visitCtlz(SDNode *N);
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SDNode *visitCttz(SDNode *N);
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SDNode *visitCtpop(SDNode *N);
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// select
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// select_cc
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// setcc
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SDNode *visitSignExtend(SDNode *N);
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SDNode *visitZeroExtend(SDNode *N);
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SDNode *visitSignExtendInReg(SDNode *N);
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SDNode *visitTruncate(SDNode *N);
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SDNode *visitSintToFP(SDNode *N);
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SDNode *visitUintToFP(SDNode *N);
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SDNode *visitFPToSint(SDNode *N);
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SDNode *visitFPToUint(SDNode *N);
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SDNode *visitFPRound(SDNode *N);
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SDNode *visitFPRoundInReg(SDNode *N);
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SDNode *visitFPExtend(SDNode *N);
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SDNode *visitFneg(SDNode *N);
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SDNode *visitFabs(SDNode *N);
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SDNode *visitExtLoad(SDNode *N);
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SDNode *visitSextLoad(SDNode *N);
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SDNode *visitZextLoad(SDNode *N);
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SDNode *visitTruncStore(SDNode *N);
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// brcond
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// brcondtwoway
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// br_cc
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// brtwoway_cc
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public:
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DAGCombiner(SelectionDAG &D)
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: DAG(D), TLI(D.getTargetLoweringInfo()), AfterLegalize(false) {
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// Add all the dag nodes to the worklist.
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WorkList.insert(WorkList.end(), D.allnodes_begin(), D.allnodes_end());
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}
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/// Run - runs the dag combiner on all nodes in the work list
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void Run(bool RunningAfterLegalize);
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};
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}
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/// MaskedValueIsZero - Return true if 'V & Mask' is known to be zero. We use
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/// this predicate to simplify operations downstream. V and Mask are known to
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/// be the same type.
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static bool MaskedValueIsZero(const SDOperand &Op, uint64_t Mask,
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const TargetLowering &TLI) {
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unsigned SrcBits;
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if (Mask == 0) return true;
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// If we know the result of a setcc has the top bits zero, use this info.
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switch (Op.getOpcode()) {
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case ISD::Constant:
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return (cast<ConstantSDNode>(Op)->getValue() & Mask) == 0;
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case ISD::SETCC:
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return ((Mask & 1) == 0) &&
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TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult;
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case ISD::ZEXTLOAD:
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SrcBits = MVT::getSizeInBits(cast<VTSDNode>(Op.getOperand(3))->getVT());
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return (Mask & ((1ULL << SrcBits)-1)) == 0; // Returning only the zext bits.
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case ISD::ZERO_EXTEND:
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SrcBits = MVT::getSizeInBits(Op.getOperand(0).getValueType());
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return MaskedValueIsZero(Op.getOperand(0),Mask & ((1ULL << SrcBits)-1),TLI);
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case ISD::AssertZext:
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SrcBits = MVT::getSizeInBits(cast<VTSDNode>(Op.getOperand(1))->getVT());
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return (Mask & ((1ULL << SrcBits)-1)) == 0; // Returning only the zext bits.
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case ISD::AND:
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// (X & C1) & C2 == 0 iff C1 & C2 == 0.
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if (ConstantSDNode *AndRHS = dyn_cast<ConstantSDNode>(Op.getOperand(1)))
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return MaskedValueIsZero(Op.getOperand(0),AndRHS->getValue() & Mask, TLI);
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// FALL THROUGH
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case ISD::OR:
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case ISD::XOR:
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return MaskedValueIsZero(Op.getOperand(0), Mask, TLI) &&
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MaskedValueIsZero(Op.getOperand(1), Mask, TLI);
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case ISD::SELECT:
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return MaskedValueIsZero(Op.getOperand(1), Mask, TLI) &&
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MaskedValueIsZero(Op.getOperand(2), Mask, TLI);
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case ISD::SELECT_CC:
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return MaskedValueIsZero(Op.getOperand(2), Mask, TLI) &&
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MaskedValueIsZero(Op.getOperand(3), Mask, TLI);
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case ISD::SRL:
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// (ushr X, C1) & C2 == 0 iff X & (C2 << C1) == 0
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if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
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uint64_t NewVal = Mask << ShAmt->getValue();
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SrcBits = MVT::getSizeInBits(Op.getValueType());
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if (SrcBits != 64) NewVal &= (1ULL << SrcBits)-1;
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return MaskedValueIsZero(Op.getOperand(0), NewVal, TLI);
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}
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return false;
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case ISD::SHL:
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// (ushl X, C1) & C2 == 0 iff X & (C2 >> C1) == 0
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if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
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uint64_t NewVal = Mask >> ShAmt->getValue();
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return MaskedValueIsZero(Op.getOperand(0), NewVal, TLI);
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}
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return false;
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case ISD::CTTZ:
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case ISD::CTLZ:
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case ISD::CTPOP:
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// Bit counting instructions can not set the high bits of the result
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// register. The max number of bits sets depends on the input.
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return (Mask & (MVT::getSizeInBits(Op.getValueType())*2-1)) == 0;
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// TODO we could handle some SRA cases here.
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default: break;
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}
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return false;
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}
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// isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc
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// that selects between the values 1 and 0, making it equivalent to a setcc.
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static bool isSetCCEquivalent(SDOperand N) {
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if (N.getOpcode() == ISD::SETCC)
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return true;
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if (N.getOpcode() == ISD::SELECT_CC &&
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N.getOperand(2).getOpcode() == ISD::Constant &&
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N.getOperand(3).getOpcode() == ISD::Constant &&
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cast<ConstantSDNode>(N.getOperand(2))->getValue() == 1 &&
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cast<ConstantSDNode>(N.getOperand(3))->isNullValue())
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return true;
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return false;
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}
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// isInvertibleForFree - Return true if there is no cost to emitting the logical
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// inverse of this node.
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static bool isInvertibleForFree(SDOperand N) {
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if (isa<ConstantSDNode>(N.Val)) return true;
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if (isSetCCEquivalent(N) && N.Val->hasOneUse())
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return true;
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return false;
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}
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void DAGCombiner::Run(bool RunningAfterLegalize) {
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// set the instance variable, so that the various visit routines may use it.
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AfterLegalize = RunningAfterLegalize;
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// while the worklist isn't empty, inspect the node on the end of it and
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// try and combine it.
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while (!WorkList.empty()) {
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SDNode *N = WorkList.back();
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WorkList.pop_back();
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// If N has no uses, it is dead. Make sure to revisit all N's operands once
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// N is deleted from the DAG, since they too may now be dead.
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if (N->use_empty()) {
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for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
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WorkList.push_back(N->getOperand(i).Val);
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DAG.DeleteNode(N);
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removeFromWorkList(N);
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continue;
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}
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if (SDNode *Result = visit(N)) {
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++NodesCombined;
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assert(Result != N && "Modifying DAG nodes in place is illegal!");
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std::cerr << "DC: Old = "; N->dump();
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std::cerr << " New = "; Result->dump();
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std::cerr << '\n';
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DAG.ReplaceAllUsesWith(N, Result);
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// Push the new node and any users onto the worklist
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WorkList.push_back(Result);
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AddUsersToWorkList(Result);
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// Nodes can end up on the worklist more than once. Make sure we do
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// not process a node that has been replaced.
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removeFromWorkList(N);
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}
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}
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}
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SDNode *DAGCombiner::visit(SDNode *N) {
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switch(N->getOpcode()) {
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default: break;
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case ISD::TokenFactor: return visitTokenFactor(N);
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case ISD::ADD: return visitAdd(N);
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case ISD::SUB: return visitSub(N);
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case ISD::MUL: return visitMul(N);
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case ISD::SDIV: return visitSdiv(N);
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case ISD::UDIV: return visitUdiv(N);
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case ISD::SREM: return visitSrem(N);
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case ISD::UREM: return visitUrem(N);
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case ISD::MULHU: return visitMulHiU(N);
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case ISD::MULHS: return visitMulHiS(N);
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case ISD::AND: return visitAnd(N);
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case ISD::OR: return visitOr(N);
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case ISD::XOR: return visitXor(N);
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case ISD::SHL: return visitShl(N);
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case ISD::SRA: return visitSra(N);
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case ISD::SRL: return visitSrl(N);
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case ISD::CTLZ: return visitCtlz(N);
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case ISD::CTTZ: return visitCttz(N);
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case ISD::CTPOP: return visitCtpop(N);
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case ISD::SIGN_EXTEND: return visitSignExtend(N);
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case ISD::ZERO_EXTEND: return visitZeroExtend(N);
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case ISD::SIGN_EXTEND_INREG: return visitSignExtendInReg(N);
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case ISD::TRUNCATE: return visitTruncate(N);
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case ISD::SINT_TO_FP: return visitSintToFP(N);
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case ISD::UINT_TO_FP: return visitUintToFP(N);
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case ISD::FP_TO_SINT: return visitFPToSint(N);
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case ISD::FP_TO_UINT: return visitFPToUint(N);
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case ISD::FP_ROUND: return visitFPRound(N);
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case ISD::FP_ROUND_INREG: return visitFPRoundInReg(N);
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case ISD::FP_EXTEND: return visitFPExtend(N);
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case ISD::FNEG: return visitFneg(N);
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case ISD::FABS: return visitFabs(N);
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}
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return 0;
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}
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SDNode *DAGCombiner::visitTokenFactor(SDNode *N) {
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// If the token factor only has one operand, fold TF(x) -> x
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if (N->getNumOperands() == 1)
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return N->getOperand(0).Val;
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// If the token factor has two operands and one is the entry token, replace
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// the token factor with the other operand.
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if (N->getNumOperands() == 2) {
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if (N->getOperand(0).getOpcode() == ISD::EntryToken)
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return N->getOperand(1).Val;
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if (N->getOperand(1).getOpcode() == ISD::EntryToken)
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return N->getOperand(0).Val;
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}
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return 0;
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}
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SDNode *DAGCombiner::visitAdd(SDNode *N) {
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SDOperand N0 = N->getOperand(0);
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SDOperand N1 = N->getOperand(1);
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ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N0);
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ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N1);
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ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N0);
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ConstantFPSDNode *N2CFP = dyn_cast<ConstantFPSDNode>(N1);
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// fold (add c1, c2) -> c1+c2
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if (N1C && N2C)
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return DAG.getConstant(N1C->getValue() + N2C->getValue(),
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N->getValueType(0)).Val;
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// fold (add x, 0) -> x
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if (N2C && N2C->isNullValue())
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return N0.Val;
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// fold floating point (add c1, c2) -> c1+c2
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if (N1CFP && N2CFP)
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return DAG.getConstantFP(N1CFP->getValue() + N2CFP->getValue(),
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N->getValueType(0)).Val;
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// fold (A + (-B)) -> A-B
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if (N1.getOpcode() == ISD::FNEG)
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return DAG.getNode(ISD::SUB, N->getValueType(0), N0, N1.getOperand(0)).Val;
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// fold ((-A) + B) -> B-A
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if (N0.getOpcode() == ISD::FNEG)
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return DAG.getNode(ISD::SUB, N->getValueType(0), N1, N0.getOperand(0)).Val;
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// fold ((0-A) + B) -> B-A
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if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) &&
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cast<ConstantSDNode>(N0.getOperand(0))->isNullValue())
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return DAG.getNode(ISD::SUB, N->getValueType(0), N1, N0.getOperand(1)).Val;
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// fold (A + (0-B)) -> A-B
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if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) &&
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cast<ConstantSDNode>(N1.getOperand(0))->isNullValue())
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return DAG.getNode(ISD::SUB, N->getValueType(0), N0, N1.getOperand(1)).Val;
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// fold (A+(B-A)) -> B for non-fp types
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if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1) &&
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!MVT::isFloatingPoint(N1.getValueType()))
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return N1.getOperand(0).Val;
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return 0;
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}
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SDNode *DAGCombiner::visitSub(SDNode *N) {
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SDOperand N0 = N->getOperand(0);
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SDOperand N1 = N->getOperand(1);
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ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N0.Val);
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ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N1.Val);
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ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N0.Val);
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ConstantFPSDNode *N2CFP = dyn_cast<ConstantFPSDNode>(N1.Val);
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// fold (sub c1, c2) -> c1-c2
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if (N1C && N2C)
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return DAG.getConstant(N1C->getValue() - N2C->getValue(),
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N->getValueType(0)).Val;
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// fold (sub x, 0) -> x
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if (N2C && N2C->isNullValue())
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return N0.Val;
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// fold floating point (sub c1, c2) -> c1-c2
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if (N1CFP && N2CFP)
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return DAG.getConstantFP(N1CFP->getValue() - N2CFP->getValue(),
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N->getValueType(0)).Val;
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// fold (A+B)-A -> B
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if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 &&
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!MVT::isFloatingPoint(N1.getValueType()))
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return N0.getOperand(1).Val;
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// fold (A+B)-B -> A
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if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1 &&
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!MVT::isFloatingPoint(N1.getValueType()))
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return N0.getOperand(0).Val;
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// fold (A-(-B)) -> A+B
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if (N1.getOpcode() == ISD::FNEG)
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return DAG.getNode(ISD::ADD, N0.getValueType(), N0, N1.getOperand(0)).Val;
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return 0;
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}
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SDNode *DAGCombiner::visitMul(SDNode *N) {
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SDOperand N0 = N->getOperand(0);
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SDOperand N1 = N->getOperand(1);
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ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N0);
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ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N1);
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ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N0);
|
|
ConstantFPSDNode *N2CFP = dyn_cast<ConstantFPSDNode>(N1);
|
|
|
|
// fold (mul c1, c2) -> c1*c2
|
|
if (N1C && N2C)
|
|
return DAG.getConstant(N1C->getValue() * N2C->getValue(),
|
|
N->getValueType(0)).Val;
|
|
// fold (mul x, 0) -> 0
|
|
if (N2C && N2C->isNullValue())
|
|
return N1.Val;
|
|
// fold (mul x, -1) -> 0-x
|
|
if (N2C && N2C->isAllOnesValue())
|
|
return DAG.getNode(ISD::SUB, N->getValueType(0),
|
|
DAG.getConstant(0, N->getValueType(0)), N0).Val;
|
|
// fold (mul x, (1 << c)) -> x << c
|
|
if (N2C && isPowerOf2_64(N2C->getValue()))
|
|
return DAG.getNode(ISD::SHL, N->getValueType(0), N0,
|
|
DAG.getConstant(Log2_64(N2C->getValue()),
|
|
TLI.getShiftAmountTy())).Val;
|
|
// fold floating point (mul c1, c2) -> c1*c2
|
|
if (N1CFP && N2CFP)
|
|
return DAG.getConstantFP(N1CFP->getValue() * N2CFP->getValue(),
|
|
N->getValueType(0)).Val;
|
|
return 0;
|
|
}
|
|
|
|
SDNode *DAGCombiner::visitSdiv(SDNode *N) {
|
|
SDOperand N0 = N->getOperand(0);
|
|
SDOperand N1 = N->getOperand(1);
|
|
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N0.Val);
|
|
ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N1.Val);
|
|
ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N0.Val);
|
|
ConstantFPSDNode *N2CFP = dyn_cast<ConstantFPSDNode>(N1.Val);
|
|
|
|
// fold (sdiv c1, c2) -> c1/c2
|
|
if (N1C && N2C)
|
|
return DAG.getConstant(N1C->getSignExtended() / N2C->getSignExtended(),
|
|
N->getValueType(0)).Val;
|
|
// fold floating point (sdiv c1, c2) -> c1/c2
|
|
if (N1CFP && N2CFP)
|
|
return DAG.getConstantFP(N1CFP->getValue() / N2CFP->getValue(),
|
|
N->getValueType(0)).Val;
|
|
return 0;
|
|
}
|
|
|
|
SDNode *DAGCombiner::visitUdiv(SDNode *N) {
|
|
SDOperand N0 = N->getOperand(0);
|
|
SDOperand N1 = N->getOperand(1);
|
|
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N0.Val);
|
|
ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N1.Val);
|
|
|
|
// fold (udiv c1, c2) -> c1/c2
|
|
if (N1C && N2C)
|
|
return DAG.getConstant(N1C->getValue() / N2C->getValue(),
|
|
N->getValueType(0)).Val;
|
|
// fold (udiv x, (1 << c)) -> x >>u c
|
|
if (N2C && isPowerOf2_64(N2C->getValue()))
|
|
return DAG.getNode(ISD::SRL, N->getValueType(0), N0,
|
|
DAG.getConstant(Log2_64(N2C->getValue()),
|
|
TLI.getShiftAmountTy())).Val;
|
|
return 0;
|
|
}
|
|
|
|
SDNode *DAGCombiner::visitSrem(SDNode *N) {
|
|
SDOperand N0 = N->getOperand(0);
|
|
SDOperand N1 = N->getOperand(1);
|
|
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N0);
|
|
ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N1);
|
|
ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N0);
|
|
ConstantFPSDNode *N2CFP = dyn_cast<ConstantFPSDNode>(N1);
|
|
|
|
// fold (srem c1, c2) -> c1%c2
|
|
if (N1C && N2C)
|
|
return DAG.getConstant(N1C->getSignExtended() % N2C->getSignExtended(),
|
|
N->getValueType(0)).Val;
|
|
// fold floating point (srem c1, c2) -> fmod(c1, c2)
|
|
if (N1CFP && N2CFP)
|
|
return DAG.getConstantFP(fmod(N1CFP->getValue(),N2CFP->getValue()),
|
|
N->getValueType(0)).Val;
|
|
return 0;
|
|
}
|
|
|
|
SDNode *DAGCombiner::visitUrem(SDNode *N) {
|
|
SDOperand N0 = N->getOperand(0);
|
|
SDOperand N1 = N->getOperand(1);
|
|
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N0);
|
|
ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N1);
|
|
|
|
// fold (urem c1, c2) -> c1%c2
|
|
if (N1C && N2C)
|
|
return DAG.getConstant(N1C->getValue() % N2C->getValue(),
|
|
N->getValueType(0)).Val;
|
|
return 0;
|
|
}
|
|
|
|
SDNode *DAGCombiner::visitMulHiS(SDNode *N) {
|
|
SDOperand N0 = N->getOperand(0);
|
|
SDOperand N1 = N->getOperand(1);
|
|
ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N1);
|
|
|
|
// fold (mulhs x, 0) -> 0
|
|
if (N2C && N2C->isNullValue())
|
|
return N1.Val;
|
|
|
|
// fold (mulhs x, 1) -> (sra x, size(x)-1)
|
|
if (N2C && N2C->getValue() == 1)
|
|
return DAG.getNode(ISD::SRA, N0.getValueType(), N0,
|
|
DAG.getConstant(MVT::getSizeInBits(N0.getValueType())-1,
|
|
TLI.getShiftAmountTy())).Val;
|
|
return 0;
|
|
}
|
|
|
|
SDNode *DAGCombiner::visitMulHiU(SDNode *N) {
|
|
SDOperand N0 = N->getOperand(0);
|
|
SDOperand N1 = N->getOperand(1);
|
|
ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N1);
|
|
|
|
// fold (mulhu x, 0) -> 0
|
|
if (N2C && N2C->isNullValue())
|
|
return N1.Val;
|
|
|
|
// fold (mulhu x, 1) -> 0
|
|
if (N2C && N2C->getValue() == 1)
|
|
return DAG.getConstant(0, N0.getValueType()).Val;
|
|
return 0;
|
|
}
|
|
|
|
SDNode *DAGCombiner::visitAnd(SDNode *N) {
|
|
SDOperand N0 = N->getOperand(0);
|
|
SDOperand N1 = N->getOperand(1);
|
|
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N0);
|
|
ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N1);
|
|
MVT::ValueType VT = N1.getValueType();
|
|
|
|
// fold (and c1, c2) -> c1&c2
|
|
if (N1C && N2C)
|
|
return DAG.getConstant(N1C->getValue() & N2C->getValue(), VT).Val;
|
|
// fold (and x, -1) -> x
|
|
if (N2C && N2C->isAllOnesValue())
|
|
return N0.Val;
|
|
// fold (and x, 0) -> 0
|
|
if (N2C && MaskedValueIsZero(N0, N2C->getValue(), TLI))
|
|
return DAG.getConstant(0, VT).Val;
|
|
// fold (and x, mask containing x) -> x
|
|
if (N2C) {
|
|
uint64_t NotC2 = ~N2C->getValue();
|
|
NotC2 &= ~0ULL >> (64-MVT::getSizeInBits(VT));
|
|
if (MaskedValueIsZero(N0, NotC2, TLI))
|
|
return N0.Val;
|
|
}
|
|
// fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1)
|
|
if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG) {
|
|
unsigned ExtendBits =
|
|
MVT::getSizeInBits(cast<VTSDNode>(N0.getOperand(1))->getVT());
|
|
if ((N2C->getValue() & (~0ULL << ExtendBits)) == 0)
|
|
return DAG.getNode(ISD::AND, VT, N0.getOperand(0), N1).Val;
|
|
}
|
|
// fold (and (or x, 0xFFFF), 0xFF) -> 0xFF
|
|
if (N0.getOpcode() == ISD::OR)
|
|
if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
|
|
if ((ORI->getValue() & N2C->getValue()) == N2C->getValue())
|
|
return N1.Val;
|
|
return 0;
|
|
}
|
|
|
|
SDNode *DAGCombiner::visitOr(SDNode *N) {
|
|
SDOperand N0 = N->getOperand(0);
|
|
SDOperand N1 = N->getOperand(1);
|
|
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N0);
|
|
ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N1);
|
|
|
|
// fold (or c1, c2) -> c1|c2
|
|
if (N1C && N2C)
|
|
return DAG.getConstant(N1C->getValue() | N2C->getValue(),
|
|
N->getValueType(0)).Val;
|
|
// fold (or x, 0) -> x
|
|
if (N2C && N2C->isNullValue())
|
|
return N0.Val;
|
|
// fold (or x, -1) -> -1
|
|
if (N2C && N2C->isAllOnesValue())
|
|
return N1.Val;
|
|
return 0;
|
|
}
|
|
|
|
SDNode *DAGCombiner::visitXor(SDNode *N) {
|
|
SDOperand N0 = N->getOperand(0);
|
|
SDOperand N1 = N->getOperand(1);
|
|
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N0);
|
|
ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N1);
|
|
MVT::ValueType VT = N0.getValueType();
|
|
|
|
// fold (xor c1, c2) -> c1^c2
|
|
if (N1C && N2C)
|
|
return DAG.getConstant(N1C->getValue() ^ N2C->getValue(), VT).Val;
|
|
// fold (xor x, 0) -> x
|
|
if (N2C && N2C->isNullValue())
|
|
return N0.Val;
|
|
// fold !(x cc y) -> (x !cc y)
|
|
if (N2C && N2C->getValue() == 1 && N0.getOpcode() == ISD::SETCC) {
|
|
bool isInt = MVT::isInteger(N0.getOperand(0).getValueType());
|
|
ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get();
|
|
return DAG.getSetCC(VT, N0.getOperand(0), N0.getOperand(1),
|
|
ISD::getSetCCInverse(CC, isInt)).Val;
|
|
}
|
|
// fold !(x cc y) -> (x !cc y)
|
|
if (N2C && N2C->getValue() == 1 && isSetCCEquivalent(N0)) {
|
|
bool isInt = MVT::isInteger(N0.getOperand(0).getValueType());
|
|
ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(4))->get();
|
|
return DAG.getSelectCC(N0.getOperand(0), N0.getOperand(1),
|
|
N0.getOperand(2), N0.getOperand(3),
|
|
ISD::getSetCCInverse(CC, isInt)).Val;
|
|
}
|
|
// fold !(x or y) -> (!x and !y) iff x or y are freely invertible
|
|
if (N2C && N2C->isAllOnesValue() && N0.getOpcode() == ISD::OR) {
|
|
SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1);
|
|
if (isInvertibleForFree(RHS) || isInvertibleForFree(LHS)) {
|
|
LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS
|
|
RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS
|
|
return DAG.getNode(ISD::AND, VT, LHS, RHS).Val;
|
|
}
|
|
}
|
|
// fold !(x and y) -> (!x or !y) iff x or y are freely invertible
|
|
if (N2C && N2C->isAllOnesValue() && N0.getOpcode() == ISD::AND) {
|
|
SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1);
|
|
if (isInvertibleForFree(RHS) || isInvertibleForFree(LHS)) {
|
|
LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS
|
|
RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS
|
|
return DAG.getNode(ISD::OR, VT, LHS, RHS).Val;
|
|
}
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
SDNode *DAGCombiner::visitShl(SDNode *N) {
|
|
SDOperand N0 = N->getOperand(0);
|
|
SDOperand N1 = N->getOperand(1);
|
|
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N0);
|
|
ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N1);
|
|
MVT::ValueType VT = N0.getValueType();
|
|
unsigned OpSizeInBits = MVT::getSizeInBits(VT);
|
|
|
|
// fold (shl c1, c2) -> c1<<c2
|
|
if (N1C && N2C)
|
|
return DAG.getConstant(N1C->getValue() << N2C->getValue(), VT).Val;
|
|
// fold (shl 0, x) -> 0
|
|
if (N1C && N1C->isNullValue())
|
|
return N0.Val;
|
|
// fold (shl x, c >= size(x)) -> undef
|
|
if (N2C && N2C->getValue() >= OpSizeInBits)
|
|
return DAG.getNode(ISD::UNDEF, VT).Val;
|
|
// fold (shl x, 0) -> x
|
|
if (N2C && N2C->isNullValue())
|
|
return N0.Val;
|
|
// if (shl x, c) is known to be zero, return 0
|
|
if (N2C && MaskedValueIsZero(N0,(~0ULL >> (64-OpSizeInBits))>>N2C->getValue(),
|
|
TLI))
|
|
return DAG.getConstant(0, VT).Val;
|
|
// fold (shl (shl x, c1), c2) -> 0 or (shl x, c1+c2)
|
|
if (N2C && N0.getOpcode() == ISD::SHL &&
|
|
N0.getOperand(1).getOpcode() == ISD::Constant) {
|
|
uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
|
|
uint64_t c2 = N2C->getValue();
|
|
if (c1 + c2 > OpSizeInBits)
|
|
return DAG.getConstant(0, VT).Val;
|
|
return DAG.getNode(ISD::SHL, VT, N0.getOperand(0),
|
|
DAG.getConstant(c1 + c2, N1.getValueType())).Val;
|
|
}
|
|
// fold (shl (srl x, c1), c2) -> (shl (and x, -1 << c1), c2-c1) or
|
|
// (srl (and x, -1 << c1), c1-c2)
|
|
if (N2C && N0.getOpcode() == ISD::SRL &&
|
|
N0.getOperand(1).getOpcode() == ISD::Constant) {
|
|
uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
|
|
uint64_t c2 = N2C->getValue();
|
|
SDOperand Mask = DAG.getNode(ISD::AND, VT, N0.getOperand(0),
|
|
DAG.getConstant(~0ULL << c1, VT));
|
|
if (c2 > c1)
|
|
return DAG.getNode(ISD::SHL, VT, Mask,
|
|
DAG.getConstant(c2-c1, N1.getValueType())).Val;
|
|
else
|
|
return DAG.getNode(ISD::SRL, VT, Mask,
|
|
DAG.getConstant(c1-c2, N1.getValueType())).Val;
|
|
}
|
|
// fold (shl (sra x, c1), c1) -> (and x, -1 << c1)
|
|
if (N2C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1))
|
|
return DAG.getNode(ISD::AND, VT, N0.getOperand(0),
|
|
DAG.getConstant(~0ULL << N2C->getValue(), VT)).Val;
|
|
return 0;
|
|
}
|
|
|
|
SDNode *DAGCombiner::visitSra(SDNode *N) {
|
|
SDOperand N0 = N->getOperand(0);
|
|
SDOperand N1 = N->getOperand(1);
|
|
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N0);
|
|
ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N1);
|
|
MVT::ValueType VT = N0.getValueType();
|
|
unsigned OpSizeInBits = MVT::getSizeInBits(VT);
|
|
|
|
// fold (sra c1, c2) -> c1>>c2
|
|
if (N1C && N2C)
|
|
return DAG.getConstant(N1C->getSignExtended() >> N2C->getValue(), VT).Val;
|
|
// fold (sra 0, x) -> 0
|
|
if (N1C && N1C->isNullValue())
|
|
return N0.Val;
|
|
// fold (sra -1, x) -> -1
|
|
if (N1C && N1C->isAllOnesValue())
|
|
return N0.Val;
|
|
// fold (sra x, c >= size(x)) -> undef
|
|
if (N2C && N2C->getValue() >= OpSizeInBits)
|
|
return DAG.getNode(ISD::UNDEF, VT).Val;
|
|
// fold (sra x, 0) -> x
|
|
if (N2C && N2C->isNullValue())
|
|
return N0.Val;
|
|
// If the sign bit is known to be zero, switch this to a SRL.
|
|
if (N2C && MaskedValueIsZero(N0, (1ULL << (OpSizeInBits-1)), TLI))
|
|
return DAG.getNode(ISD::SRL, VT, N0, N1).Val;
|
|
return 0;
|
|
}
|
|
|
|
SDNode *DAGCombiner::visitSrl(SDNode *N) {
|
|
SDOperand N0 = N->getOperand(0);
|
|
SDOperand N1 = N->getOperand(1);
|
|
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N0);
|
|
ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N1);
|
|
MVT::ValueType VT = N0.getValueType();
|
|
unsigned OpSizeInBits = MVT::getSizeInBits(VT);
|
|
|
|
// fold (srl c1, c2) -> c1 >>u c2
|
|
if (N1C && N2C)
|
|
return DAG.getConstant(N1C->getValue() >> N2C->getValue(), VT).Val;
|
|
// fold (srl 0, x) -> 0
|
|
if (N1C && N1C->isNullValue())
|
|
return N0.Val;
|
|
// fold (srl x, c >= size(x)) -> undef
|
|
if (N2C && N2C->getValue() >= OpSizeInBits)
|
|
return DAG.getNode(ISD::UNDEF, VT).Val;
|
|
// fold (srl x, 0) -> x
|
|
if (N2C && N2C->isNullValue())
|
|
return N0.Val;
|
|
// if (srl x, c) is known to be zero, return 0
|
|
if (N2C && MaskedValueIsZero(N0,(~0ULL >> (64-OpSizeInBits))<<N2C->getValue(),
|
|
TLI))
|
|
return DAG.getConstant(0, VT).Val;
|
|
// fold (srl (srl x, c1), c2) -> 0 or (srl x, c1+c2)
|
|
if (N2C && N0.getOpcode() == ISD::SRL &&
|
|
N0.getOperand(1).getOpcode() == ISD::Constant) {
|
|
uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
|
|
uint64_t c2 = N2C->getValue();
|
|
if (c1 + c2 > OpSizeInBits)
|
|
return DAG.getConstant(0, VT).Val;
|
|
return DAG.getNode(ISD::SRL, VT, N0.getOperand(0),
|
|
DAG.getConstant(c1 + c2, N1.getValueType())).Val;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
SDNode *DAGCombiner::visitCtlz(SDNode *N) {
|
|
SDOperand N0 = N->getOperand(0);
|
|
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N0);
|
|
|
|
// fold (ctlz c1) -> c2
|
|
if (N1C)
|
|
return DAG.getConstant(CountLeadingZeros_64(N1C->getValue()),
|
|
N0.getValueType()).Val;
|
|
return 0;
|
|
}
|
|
|
|
SDNode *DAGCombiner::visitCttz(SDNode *N) {
|
|
SDOperand N0 = N->getOperand(0);
|
|
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N0);
|
|
|
|
// fold (cttz c1) -> c2
|
|
if (N1C)
|
|
return DAG.getConstant(CountTrailingZeros_64(N1C->getValue()),
|
|
N0.getValueType()).Val;
|
|
return 0;
|
|
}
|
|
|
|
SDNode *DAGCombiner::visitCtpop(SDNode *N) {
|
|
SDOperand N0 = N->getOperand(0);
|
|
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N0);
|
|
|
|
// fold (ctpop c1) -> c2
|
|
if (N1C)
|
|
return DAG.getConstant(CountPopulation_64(N1C->getValue()),
|
|
N0.getValueType()).Val;
|
|
return 0;
|
|
}
|
|
|
|
SDNode *DAGCombiner::visitSignExtend(SDNode *N) {
|
|
SDOperand N0 = N->getOperand(0);
|
|
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N0);
|
|
MVT::ValueType VT = N->getValueType(0);
|
|
|
|
// fold (sext c1) -> c1
|
|
if (N1C)
|
|
return DAG.getConstant(N1C->getSignExtended(), VT).Val;
|
|
// fold (sext (sext x)) -> (sext x)
|
|
if (N0.getOpcode() == ISD::SIGN_EXTEND)
|
|
return DAG.getNode(ISD::SIGN_EXTEND, VT, N0.getOperand(0)).Val;
|
|
return 0;
|
|
}
|
|
|
|
SDNode *DAGCombiner::visitZeroExtend(SDNode *N) {
|
|
SDOperand N0 = N->getOperand(0);
|
|
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N0);
|
|
MVT::ValueType VT = N->getValueType(0);
|
|
|
|
// fold (zext c1) -> c1
|
|
if (N1C)
|
|
return DAG.getConstant(N1C->getValue(), VT).Val;
|
|
// fold (zext (zext x)) -> (zext x)
|
|
if (N0.getOpcode() == ISD::ZERO_EXTEND)
|
|
return DAG.getNode(ISD::ZERO_EXTEND, VT, N0.getOperand(0)).Val;
|
|
return 0;
|
|
}
|
|
|
|
SDNode *DAGCombiner::visitSignExtendInReg(SDNode *N) {
|
|
SDOperand N0 = N->getOperand(0);
|
|
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N0);
|
|
MVT::ValueType VT = N->getValueType(0);
|
|
MVT::ValueType EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
|
|
|
|
// fold (sext_in_reg c1) -> c1
|
|
if (N1C) {
|
|
SDOperand Truncate = DAG.getConstant(N1C->getValue(), EVT);
|
|
return DAG.getNode(ISD::SIGN_EXTEND, VT, Truncate).Val;
|
|
}
|
|
// fold (sext_in_reg (sext_in_reg x)) -> (sext_in_reg x)
|
|
if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
|
|
cast<VTSDNode>(N0.getOperand(1))->getVT() <= EVT) {
|
|
return N0.Val;
|
|
}
|
|
// fold (sext_in_reg (assert_sext x)) -> (assert_sext x)
|
|
if (N0.getOpcode() == ISD::AssertSext &&
|
|
cast<VTSDNode>(N0.getOperand(1))->getVT() <= EVT) {
|
|
return N0.Val;
|
|
}
|
|
// fold (sext_in_reg (sextload x)) -> (sextload x)
|
|
if (N0.getOpcode() == ISD::SEXTLOAD &&
|
|
cast<VTSDNode>(N0.getOperand(3))->getVT() <= EVT) {
|
|
return N0.Val;
|
|
}
|
|
// fold (sext_in_reg (setcc x)) -> setcc x iff (setcc x) == 0 or -1
|
|
if (N0.getOpcode() == ISD::SETCC &&
|
|
TLI.getSetCCResultContents() ==
|
|
TargetLowering::ZeroOrNegativeOneSetCCResult)
|
|
return N0.Val;
|
|
// FIXME: this code is currently just ported over from SelectionDAG.cpp
|
|
// we probably actually want to handle this in two pieces. Rather than
|
|
// checking all the top bits for zero, just check the sign bit here and turn
|
|
// it into a zero extend inreg (AND with constant).
|
|
// then, let the code for AND figure out if the mask is superfluous rather
|
|
// than doing so here.
|
|
if (N0.getOpcode() == ISD::AND &&
|
|
N0.getOperand(1).getOpcode() == ISD::Constant) {
|
|
uint64_t Mask = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
|
|
unsigned NumBits = MVT::getSizeInBits(EVT);
|
|
if ((Mask & (~0ULL << (NumBits-1))) == 0)
|
|
return N0.Val;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
SDNode *DAGCombiner::visitTruncate(SDNode *N) {
|
|
SDOperand N0 = N->getOperand(0);
|
|
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N0);
|
|
MVT::ValueType VT = N->getValueType(0);
|
|
|
|
// noop truncate
|
|
if (N0.getValueType() == N->getValueType(0))
|
|
return N0.Val;
|
|
// fold (truncate c1) -> c1
|
|
if (N1C)
|
|
return DAG.getConstant(N1C->getValue(), VT).Val;
|
|
// fold (truncate (truncate x)) -> (truncate x)
|
|
if (N0.getOpcode() == ISD::TRUNCATE)
|
|
return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0)).Val;
|
|
// fold (truncate (ext x)) -> (ext x) or (truncate x) or x
|
|
if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::SIGN_EXTEND){
|
|
if (N0.getValueType() < VT)
|
|
// if the source is smaller than the dest, we still need an extend
|
|
return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0)).Val;
|
|
else if (N0.getValueType() > VT)
|
|
// if the source is larger than the dest, than we just need the truncate
|
|
return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0)).Val;
|
|
else
|
|
// if the source and dest are the same type, we can drop both the extend
|
|
// and the truncate
|
|
return N0.getOperand(0).Val;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
SDNode *DAGCombiner::visitSintToFP(SDNode *N) {
|
|
SDOperand N0 = N->getOperand(0);
|
|
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N0);
|
|
MVT::ValueType VT = N->getValueType(0);
|
|
|
|
// fold (sint_to_fp c1) -> c1fp
|
|
if (N1C)
|
|
return DAG.getConstantFP(N1C->getSignExtended(), VT).Val;
|
|
return 0;
|
|
}
|
|
|
|
SDNode *DAGCombiner::visitUintToFP(SDNode *N) {
|
|
SDOperand N0 = N->getOperand(0);
|
|
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N0);
|
|
MVT::ValueType VT = N->getValueType(0);
|
|
|
|
// fold (uint_to_fp c1) -> c1fp
|
|
if (N1C)
|
|
return DAG.getConstantFP(N1C->getValue(), VT).Val;
|
|
return 0;
|
|
}
|
|
|
|
SDNode *DAGCombiner::visitFPToSint(SDNode *N) {
|
|
ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0));
|
|
|
|
// fold (fp_to_sint c1fp) -> c1
|
|
if (N1CFP)
|
|
return DAG.getConstant((int64_t)N1CFP->getValue(), N->getValueType(0)).Val;
|
|
return 0;
|
|
}
|
|
|
|
SDNode *DAGCombiner::visitFPToUint(SDNode *N) {
|
|
ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0));
|
|
|
|
// fold (fp_to_uint c1fp) -> c1
|
|
if (N1CFP)
|
|
return DAG.getConstant((uint64_t)N1CFP->getValue(), N->getValueType(0)).Val;
|
|
return 0;
|
|
}
|
|
|
|
SDNode *DAGCombiner::visitFPRound(SDNode *N) {
|
|
ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0));
|
|
|
|
// fold (fp_round c1fp) -> c1fp
|
|
if (N1CFP)
|
|
return DAG.getConstantFP(N1CFP->getValue(), N->getValueType(0)).Val;
|
|
return 0;
|
|
}
|
|
|
|
SDNode *DAGCombiner::visitFPRoundInReg(SDNode *N) {
|
|
SDOperand N0 = N->getOperand(0);
|
|
MVT::ValueType VT = N->getValueType(0);
|
|
MVT::ValueType EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
|
|
ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N0);
|
|
|
|
// noop fp_round_inreg
|
|
if (EVT == VT)
|
|
return N0.Val;
|
|
// fold (fp_round_inreg c1fp) -> c1fp
|
|
if (N1CFP) {
|
|
SDOperand Round = DAG.getConstantFP(N1CFP->getValue(), EVT);
|
|
return DAG.getNode(ISD::FP_EXTEND, VT, Round).Val;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
SDNode *DAGCombiner::visitFPExtend(SDNode *N) {
|
|
ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0));
|
|
|
|
// fold (fp_extend c1fp) -> c1fp
|
|
if (N1CFP)
|
|
return DAG.getConstantFP(N1CFP->getValue(), N->getValueType(0)).Val;
|
|
return 0;
|
|
}
|
|
|
|
SDNode *DAGCombiner::visitFneg(SDNode *N) {
|
|
ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0));
|
|
// fold (neg c1) -> -c1
|
|
if (N1CFP)
|
|
return DAG.getConstantFP(-N1CFP->getValue(), N->getValueType(0)).Val;
|
|
// fold (neg (sub x, y)) -> (sub y, x)
|
|
if (N->getOperand(0).getOpcode() == ISD::SUB)
|
|
return DAG.getNode(ISD::SUB, N->getValueType(0), N->getOperand(1),
|
|
N->getOperand(0)).Val;
|
|
// fold (neg (neg x)) -> x
|
|
if (N->getOperand(0).getOpcode() == ISD::FNEG)
|
|
return N->getOperand(0).getOperand(0).Val;
|
|
return 0;
|
|
}
|
|
|
|
SDNode *DAGCombiner::visitFabs(SDNode *N) {
|
|
ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0));
|
|
// fold (fabs c1) -> fabs(c1)
|
|
if (N1CFP)
|
|
return DAG.getConstantFP(fabs(N1CFP->getValue()), N->getValueType(0)).Val;
|
|
// fold (fabs (fabs x)) -> (fabs x)
|
|
if (N->getOperand(0).getOpcode() == ISD::FABS)
|
|
return N->getOperand(0).Val;
|
|
// fold (fabs (fneg x)) -> (fabs x)
|
|
if (N->getOperand(0).getOpcode() == ISD::FNEG)
|
|
return DAG.getNode(ISD::FABS, N->getValueType(0),
|
|
N->getOperand(0).getOperand(0)).Val;
|
|
return 0;
|
|
}
|
|
|
|
// SelectionDAG::Combine - This is the entry point for the file.
|
|
//
|
|
void SelectionDAG::Combine(bool RunningAfterLegalize) {
|
|
/// run - This is the main entry point to this class.
|
|
///
|
|
DAGCombiner(*this).Run(RunningAfterLegalize);
|
|
}
|