6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-07-29 10:25:12 +00:00
Code Issues Projects Releases Wiki Activity

Have TargetRegisterInfo::getLargestLegalSuperClass take a

Browse Source 
MachineFunction argument so that it can look up the subtarget
rather than using a cached one in some Targets.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231888 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Eric Christopher
2015-03-10 23:46:01 +00:00
parent b8de3287ee
commit 4ec858ec4b
13 changed files with 33 additions and 24 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
lib/CodeGen/RegAllocGreedy.cpp
View File

@@ -1554,7 +1554,8 @@ RAGreedy::tryInstructionSplit(LiveInterval &VirtReg, AllocationOrder &Order,
DEBUG(dbgs() << "Split around " << Uses.size() << " individual instrs.\n");
const TargetRegisterClass *SuperRC = TRI->getLargestLegalSuperClass(CurRC);
const TargetRegisterClass *SuperRC =
TRI->getLargestLegalSuperClass(CurRC, *MF);
unsigned SuperRCNumAllocatableRegs = RCI.getNumAllocatableRegs(SuperRC);
// Split around every non-copy instruction if this split will relax
// the constraints on the virtual register.