6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-12-13 04:30:23 +00:00
Code Issues Projects Releases Wiki Activity

Document -mcpu -mattr -triple

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24731 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2005-12-16 05:18:53 +00:00
parent 3015e6061c
commit 4f501bf322
2 changed files with 45 additions and 18 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

36
docs/CommandGuide/llc.pod
View File

@ -46,11 +46,31 @@ Print a summary of command line options.
Overwrite output files. By default, B<llc> will refuse to overwrite
an output file which already exists.
=item B<-triple>=I<target triple>
Override the target triple specified in the input bytecode file with the
specified string.
=item B<-march>=I<arch>
Specify the architecture for which to generate assembly, overriding the target
encoded in the bytecode file. See the output of B<llc --help> for a list of
valid architectures.
valid architectures. By default this is inferred from the target triple or
autodetected to the current architecture.
=item B<-mcpu>=I<cpuname>
Specify a specific chip in the current architecture to generate code for.
By default this is inferred from the target triple and autodetected to
the current architecture. For a list of available CPUs, use:
B<llvm-as E<lt> /dev/null | llc -march=xyz -mcpu=help>
=item B<-mattr>=I<a1,+a2,-a3,...>
Override or control specific attributes of the target, such as whether SIMD
operations are enabled or not. The default set of attributes is set by the
current CPU. For a list of available attributes, use:
B<llvm-as E<lt> /dev/null | llc -march=xyz -mattr=help>
=item B<--disable-fp-elim>
@ -155,20 +175,6 @@ syntax.
=back
=head2 SPARCV9-specific Options
=over
=item B<--disable-peephole>
Disable peephole optimization pass.
=item B<--disable-sched>
Disable local scheduling pass.
=back
=head1 EXIT STATUS
If B<llc> succeeds, it will exit with 0. Otherwise, if an error occurs,

27
docs/CommandGuide/lli.pod
View File

@ -40,11 +40,32 @@ the just-in-time compiler, at present.
Record the amount of time needed for each code-generation pass and print it to
standard error.
=item B<-triple>=I<target triple>
Override the target triple specified in the input bytecode file with the
specified string. This may result in a crash if you pick an
architecture which is not compatible with the current system.
=item B<-march>=I<arch>
Use the specified non-default architecture arch when selecting a code generator
for the just-in-time compiler. This may result in a crash if you pick an
architecture which is not compatible with the hardware you are running B<lli> on.
Specify the architecture for which to generate assembly, overriding the target
encoded in the bytecode file. See the output of B<llc --help> for a list of
valid architectures. By default this is inferred from the target triple or
autodetected to the current architecture.
=item B<-mcpu>=I<cpuname>
Specify a specific chip in the current architecture to generate code for.
By default this is inferred from the target triple and autodetected to
the current architecture. For a list of available CPUs, use:
B<llvm-as E<lt> /dev/null | llc -march=xyz -mcpu=help>
=item B<-mattr>=I<a1,+a2,-a3,...>
Override or control specific attributes of the target, such as whether SIMD
operations are enabled or not. The default set of attributes is set by the
current CPU. For a list of available attributes, use:
B<llvm-as E<lt> /dev/null | llc -march=xyz -mattr=help>
=item B<-force-interpreter>=I<{false,true}>