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Widen the instruction encoder that TblGen emits to a 64 bits, which should accomodate every target I can think of offhand.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148833 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Owen Anderson
2012-01-24 18:37:29 +00:00
parent e983a134e7
commit 4f8dc7b17a
8 changed files with 14 additions and 14 deletions
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2
lib/Target/ARM/ARMCodeEmitter.cpp
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@@ -74,7 +74,7 @@ namespace {
/// getBinaryCodeForInstr - This function, generated by the
/// CodeEmitterGenerator using TableGen, produces the binary encoding for
/// machine instructions.
unsigned getBinaryCodeForInstr(const MachineInstr &MI) const;
uint64_t getBinaryCodeForInstr(const MachineInstr &MI) const;
bool runOnMachineFunction(MachineFunction &MF);

2
lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
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@@ -64,7 +64,7 @@ public:
// getBinaryCodeForInstr - TableGen'erated function for getting the
// binary encoding for an instruction.
unsigned getBinaryCodeForInstr(const MCInst &MI,
uint64_t getBinaryCodeForInstr(const MCInst &MI,
SmallVectorImpl<MCFixup> &Fixups) const;
/// getMachineOpValue - Return binary encoding of operand. If the machine