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Widen the instruction encoder that TblGen emits to a 64 bits, which should accomodate every target I can think of offhand.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148833 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Owen Anderson
2012-01-24 18:37:29 +00:00
parent e983a134e7
commit 4f8dc7b17a
8 changed files with 14 additions and 14 deletions
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utils/TableGen/CodeEmitterGen.cpp
+7 -7
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@@ -169,13 +169,13 @@ AddCodeToMergeInOperand(Record *R, BitsInit *BI, const std::string &VarName,
opShift = beginInstBit - beginVarBit;
if (opShift > 0) {
Case += " Value |= (op & " + utostr(opMask) + "U) << " +
Case += " Value |= (op & UINT64_C(" + utostr(opMask) + ")) << " +
itostr(opShift) + ";\n";
} else if (opShift < 0) {
Case += " Value |= (op & " + utostr(opMask) + "U) >> " +
Case += " Value |= (op & UINT64_C(" + utostr(opMask) + ")) >> " +
itostr(-opShift) + ";\n";
} else {
Case += " Value |= op & " + utostr(opMask) + "U;\n";
Case += " Value |= op & UINT64_C(" + utostr(opMask) + ");\n";
}
}
}
@@ -220,7 +220,7 @@ void CodeEmitterGen::run(raw_ostream &o) {
Target.getInstructionsByEnumValue();
// Emit function declaration
o << "unsigned " << Target.getName();
o << "uint64_t " << Target.getName();
if (MCEmitter)
o << "MCCodeEmitter::getBinaryCodeForInstr(const MCInst &MI,\n"
<< " SmallVectorImpl<MCFixup> &Fixups) const {\n";
@@ -238,7 +238,7 @@ void CodeEmitterGen::run(raw_ostream &o) {
if (R->getValueAsString("Namespace") == "TargetOpcode" ||
R->getValueAsBit("isPseudo")) {
o << " 0U,\n";
o << " UINT64_C(0),\n";
continue;
}
@@ -250,9 +250,9 @@ void CodeEmitterGen::run(raw_ostream &o) {
if (BitInit *B = dynamic_cast<BitInit*>(BI->getBit(e-i-1)))
Value |= B->getValue() << (e-i-1);
}
o << " " << Value << "U," << '\t' << "// " << R->getName() << "\n";
o << " UINT64_C(" << Value << ")," << '\t' << "// " << R->getName() << "\n";
}
o << " 0U\n };\n";
o << " UINT64_C(0)\n };\n";
// Map to accumulate all the cases.
std::map<std::string, std::vector<std::string> > CaseMap;