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Propagate MCSubtargetInfo through TableGen's getBinaryCodeForInstr()

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200349 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
David Woodhouse 2014-01-28 23:13:18 +00:00
parent 2ddea4b44d
commit 4faa861f19
10 changed files with 555 additions and 315 deletions
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144
lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp
View File

@ -39,72 +39,92 @@ public:
~AArch64MCCodeEmitter() {} ~AArch64MCCodeEmitter() {}
unsigned getAddSubImmOpValue(const MCInst &MI, unsigned OpIdx, unsigned getAddSubImmOpValue(const MCInst &MI, unsigned OpIdx,
SmallVectorImpl<MCFixup> &Fixups) const; SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
unsigned getAdrpLabelOpValue(const MCInst &MI, unsigned OpIdx, unsigned getAdrpLabelOpValue(const MCInst &MI, unsigned OpIdx,
SmallVectorImpl<MCFixup> &Fixups) const; SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
template<int MemSize> template<int MemSize>
unsigned getOffsetUImm12OpValue(const MCInst &MI, unsigned OpIdx, unsigned getOffsetUImm12OpValue(const MCInst &MI, unsigned OpIdx,
SmallVectorImpl<MCFixup> &Fixups) const { SmallVectorImpl<MCFixup> &Fixups,
return getOffsetUImm12OpValue(MI, OpIdx, Fixups, MemSize); const MCSubtargetInfo &STI) const {
return getOffsetUImm12OpValue(MI, OpIdx, Fixups, STI, MemSize);
} }
unsigned getOffsetUImm12OpValue(const MCInst &MI, unsigned OpIdx, unsigned getOffsetUImm12OpValue(const MCInst &MI, unsigned OpIdx,
SmallVectorImpl<MCFixup> &Fixups, SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI,
int MemSize) const; int MemSize) const;
unsigned getBitfield32LSLOpValue(const MCInst &MI, unsigned OpIdx, unsigned getBitfield32LSLOpValue(const MCInst &MI, unsigned OpIdx,
SmallVectorImpl<MCFixup> &Fixups) const; SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
unsigned getBitfield64LSLOpValue(const MCInst &MI, unsigned OpIdx, unsigned getBitfield64LSLOpValue(const MCInst &MI, unsigned OpIdx,
SmallVectorImpl<MCFixup> &Fixups) const; SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
unsigned getShiftRightImm8(const MCInst &MI, unsigned Op, unsigned getShiftRightImm8(const MCInst &MI, unsigned Op,
SmallVectorImpl<MCFixup> &Fixups) const; SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
unsigned getShiftRightImm16(const MCInst &MI, unsigned Op, unsigned getShiftRightImm16(const MCInst &MI, unsigned Op,
SmallVectorImpl<MCFixup> &Fixups) const; SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
unsigned getShiftRightImm32(const MCInst &MI, unsigned Op, unsigned getShiftRightImm32(const MCInst &MI, unsigned Op,
SmallVectorImpl<MCFixup> &Fixups) const; SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
unsigned getShiftRightImm64(const MCInst &MI, unsigned Op, unsigned getShiftRightImm64(const MCInst &MI, unsigned Op,
SmallVectorImpl<MCFixup> &Fixups) const; SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
unsigned getShiftLeftImm8(const MCInst &MI, unsigned Op, unsigned getShiftLeftImm8(const MCInst &MI, unsigned Op,
SmallVectorImpl<MCFixup> &Fixups) const; SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
unsigned getShiftLeftImm16(const MCInst &MI, unsigned Op, unsigned getShiftLeftImm16(const MCInst &MI, unsigned Op,
SmallVectorImpl<MCFixup> &Fixups) const; SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
unsigned getShiftLeftImm32(const MCInst &MI, unsigned Op, unsigned getShiftLeftImm32(const MCInst &MI, unsigned Op,
SmallVectorImpl<MCFixup> &Fixups) const; SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
unsigned getShiftLeftImm64(const MCInst &MI, unsigned Op, unsigned getShiftLeftImm64(const MCInst &MI, unsigned Op,
SmallVectorImpl<MCFixup> &Fixups) const; SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
// Labels are handled mostly the same way: a symbol is needed, and // Labels are handled mostly the same way: a symbol is needed, and
// just gets some fixup attached. // just gets some fixup attached.
template<AArch64::Fixups fixupDesired> template<AArch64::Fixups fixupDesired>
unsigned getLabelOpValue(const MCInst &MI, unsigned OpIdx, unsigned getLabelOpValue(const MCInst &MI, unsigned OpIdx,
SmallVectorImpl<MCFixup> &Fixups) const; SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
unsigned getLoadLitLabelOpValue(const MCInst &MI, unsigned OpIdx, unsigned getLoadLitLabelOpValue(const MCInst &MI, unsigned OpIdx,
SmallVectorImpl<MCFixup> &Fixups) const; SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
unsigned getMoveWideImmOpValue(const MCInst &MI, unsigned OpIdx, unsigned getMoveWideImmOpValue(const MCInst &MI, unsigned OpIdx,
SmallVectorImpl<MCFixup> &Fixups) const; SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
unsigned getAddressWithFixup(const MCOperand &MO, unsigned getAddressWithFixup(const MCOperand &MO,
unsigned FixupKind, unsigned FixupKind,
SmallVectorImpl<MCFixup> &Fixups) const; SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
// getBinaryCodeForInstr - TableGen'erated function for getting the // getBinaryCodeForInstr - TableGen'erated function for getting the
// binary encoding for an instruction. // binary encoding for an instruction.
uint64_t getBinaryCodeForInstr(const MCInst &MI, uint64_t getBinaryCodeForInstr(const MCInst &MI,
SmallVectorImpl<MCFixup> &Fixups) const; SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
/// getMachineOpValue - Return binary encoding of operand. If the machine /// getMachineOpValue - Return binary encoding of operand. If the machine
/// operand requires relocation, record the relocation and return zero. /// operand requires relocation, record the relocation and return zero.
unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO, unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO,
SmallVectorImpl<MCFixup> &Fixups) const; SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
void EmitByte(unsigned char C, raw_ostream &OS) const { void EmitByte(unsigned char C, raw_ostream &OS) const {
@ -125,11 +145,14 @@ public:
const MCSubtargetInfo &STI) const; const MCSubtargetInfo &STI) const;
template<int hasRs, int hasRt2> unsigned template<int hasRs, int hasRt2> unsigned
fixLoadStoreExclusive(const MCInst &MI, unsigned EncodedValue) const; fixLoadStoreExclusive(const MCInst &MI, unsigned EncodedValue,
const MCSubtargetInfo &STI) const;
unsigned fixMOVZ(const MCInst &MI, unsigned EncodedValue) const; unsigned fixMOVZ(const MCInst &MI, unsigned EncodedValue,
const MCSubtargetInfo &STI) const;
unsigned fixMulHigh(const MCInst &MI, unsigned EncodedValue) const; unsigned fixMulHigh(const MCInst &MI, unsigned EncodedValue,
const MCSubtargetInfo &STI) const;
}; };
@ -138,7 +161,8 @@ public:
unsigned AArch64MCCodeEmitter::getAddressWithFixup(const MCOperand &MO, unsigned AArch64MCCodeEmitter::getAddressWithFixup(const MCOperand &MO,
unsigned FixupKind, unsigned FixupKind,
SmallVectorImpl<MCFixup> &Fixups) const { SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
if (!MO.isExpr()) { if (!MO.isExpr()) {
// This can occur for manually decoded or constructed MCInsts, but neither // This can occur for manually decoded or constructed MCInsts, but neither
// the assembly-parser nor instruction selection will currently produce an // the assembly-parser nor instruction selection will currently produce an
@ -157,6 +181,7 @@ unsigned AArch64MCCodeEmitter::getAddressWithFixup(const MCOperand &MO,
unsigned AArch64MCCodeEmitter:: unsigned AArch64MCCodeEmitter::
getOffsetUImm12OpValue(const MCInst &MI, unsigned OpIdx, getOffsetUImm12OpValue(const MCInst &MI, unsigned OpIdx,
SmallVectorImpl<MCFixup> &Fixups, SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI,
int MemSize) const { int MemSize) const {
const MCOperand &ImmOp = MI.getOperand(OpIdx); const MCOperand &ImmOp = MI.getOperand(OpIdx);
if (ImmOp.isImm()) if (ImmOp.isImm())
@ -237,12 +262,13 @@ getOffsetUImm12OpValue(const MCInst &MI, unsigned OpIdx,
break; break;
} }
return getAddressWithFixup(ImmOp, FixupKind, Fixups); return getAddressWithFixup(ImmOp, FixupKind, Fixups, STI);
} }
unsigned unsigned
AArch64MCCodeEmitter::getAddSubImmOpValue(const MCInst &MI, unsigned OpIdx, AArch64MCCodeEmitter::getAddSubImmOpValue(const MCInst &MI, unsigned OpIdx,
SmallVectorImpl<MCFixup> &Fixups) const { SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
const MCOperand &MO = MI.getOperand(OpIdx); const MCOperand &MO = MI.getOperand(OpIdx);
if (MO.isImm()) if (MO.isImm())
return static_cast<unsigned>(MO.getImm()); return static_cast<unsigned>(MO.getImm());
@ -270,12 +296,13 @@ AArch64MCCodeEmitter::getAddSubImmOpValue(const MCInst &MI, unsigned OpIdx,
FixupKind = AArch64::fixup_a64_tlsdesc_add_lo12_nc; break; FixupKind = AArch64::fixup_a64_tlsdesc_add_lo12_nc; break;
} }
return getAddressWithFixup(MO, FixupKind, Fixups); return getAddressWithFixup(MO, FixupKind, Fixups, STI);
} }
unsigned unsigned
AArch64MCCodeEmitter::getAdrpLabelOpValue(const MCInst &MI, unsigned OpIdx, AArch64MCCodeEmitter::getAdrpLabelOpValue(const MCInst &MI, unsigned OpIdx,
SmallVectorImpl<MCFixup> &Fixups) const { SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
const MCOperand &MO = MI.getOperand(OpIdx); const MCOperand &MO = MI.getOperand(OpIdx);
if (MO.isImm()) if (MO.isImm())
@ -305,12 +332,13 @@ AArch64MCCodeEmitter::getAdrpLabelOpValue(const MCInst &MI, unsigned OpIdx,
llvm_unreachable("Unknown symbol reference kind for ADRP instruction"); llvm_unreachable("Unknown symbol reference kind for ADRP instruction");
} }
return getAddressWithFixup(MO, FixupKind, Fixups); return getAddressWithFixup(MO, FixupKind, Fixups, STI);
} }
unsigned unsigned
AArch64MCCodeEmitter::getBitfield32LSLOpValue(const MCInst &MI, unsigned OpIdx, AArch64MCCodeEmitter::getBitfield32LSLOpValue(const MCInst &MI, unsigned OpIdx,
SmallVectorImpl<MCFixup> &Fixups) const { SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
const MCOperand &MO = MI.getOperand(OpIdx); const MCOperand &MO = MI.getOperand(OpIdx);
assert(MO.isImm() && "Only immediate expected for shift"); assert(MO.isImm() && "Only immediate expected for shift");
@ -320,7 +348,8 @@ AArch64MCCodeEmitter::getBitfield32LSLOpValue(const MCInst &MI, unsigned OpIdx,
unsigned unsigned
AArch64MCCodeEmitter::getBitfield64LSLOpValue(const MCInst &MI, unsigned OpIdx, AArch64MCCodeEmitter::getBitfield64LSLOpValue(const MCInst &MI, unsigned OpIdx,
SmallVectorImpl<MCFixup> &Fixups) const { SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
const MCOperand &MO = MI.getOperand(OpIdx); const MCOperand &MO = MI.getOperand(OpIdx);
assert(MO.isImm() && "Only immediate expected for shift"); assert(MO.isImm() && "Only immediate expected for shift");
@ -329,53 +358,62 @@ AArch64MCCodeEmitter::getBitfield64LSLOpValue(const MCInst &MI, unsigned OpIdx,
} }
unsigned AArch64MCCodeEmitter::getShiftRightImm8( unsigned AArch64MCCodeEmitter::getShiftRightImm8(
const MCInst &MI, unsigned Op, SmallVectorImpl<MCFixup> &Fixups) const { const MCInst &MI, unsigned Op, SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
return 8 - MI.getOperand(Op).getImm(); return 8 - MI.getOperand(Op).getImm();
} }
unsigned AArch64MCCodeEmitter::getShiftRightImm16( unsigned AArch64MCCodeEmitter::getShiftRightImm16(
const MCInst &MI, unsigned Op, SmallVectorImpl<MCFixup> &Fixups) const { const MCInst &MI, unsigned Op, SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
return 16 - MI.getOperand(Op).getImm(); return 16 - MI.getOperand(Op).getImm();
} }
unsigned AArch64MCCodeEmitter::getShiftRightImm32( unsigned AArch64MCCodeEmitter::getShiftRightImm32(
const MCInst &MI, unsigned Op, SmallVectorImpl<MCFixup> &Fixups) const { const MCInst &MI, unsigned Op, SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
return 32 - MI.getOperand(Op).getImm(); return 32 - MI.getOperand(Op).getImm();
} }
unsigned AArch64MCCodeEmitter::getShiftRightImm64( unsigned AArch64MCCodeEmitter::getShiftRightImm64(
const MCInst &MI, unsigned Op, SmallVectorImpl<MCFixup> &Fixups) const { const MCInst &MI, unsigned Op, SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
return 64 - MI.getOperand(Op).getImm(); return 64 - MI.getOperand(Op).getImm();
} }
unsigned AArch64MCCodeEmitter::getShiftLeftImm8( unsigned AArch64MCCodeEmitter::getShiftLeftImm8(
const MCInst &MI, unsigned Op, SmallVectorImpl<MCFixup> &Fixups) const { const MCInst &MI, unsigned Op, SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
return MI.getOperand(Op).getImm() - 8; return MI.getOperand(Op).getImm() - 8;
} }
unsigned AArch64MCCodeEmitter::getShiftLeftImm16( unsigned AArch64MCCodeEmitter::getShiftLeftImm16(
const MCInst &MI, unsigned Op, SmallVectorImpl<MCFixup> &Fixups) const { const MCInst &MI, unsigned Op, SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
return MI.getOperand(Op).getImm() - 16; return MI.getOperand(Op).getImm() - 16;
} }
unsigned AArch64MCCodeEmitter::getShiftLeftImm32( unsigned AArch64MCCodeEmitter::getShiftLeftImm32(
const MCInst &MI, unsigned Op, SmallVectorImpl<MCFixup> &Fixups) const { const MCInst &MI, unsigned Op, SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
return MI.getOperand(Op).getImm() - 32; return MI.getOperand(Op).getImm() - 32;
} }
unsigned AArch64MCCodeEmitter::getShiftLeftImm64( unsigned AArch64MCCodeEmitter::getShiftLeftImm64(
const MCInst &MI, unsigned Op, SmallVectorImpl<MCFixup> &Fixups) const { const MCInst &MI, unsigned Op, SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
return MI.getOperand(Op).getImm() - 64; return MI.getOperand(Op).getImm() - 64;
} }
template<AArch64::Fixups fixupDesired> unsigned template<AArch64::Fixups fixupDesired> unsigned
AArch64MCCodeEmitter::getLabelOpValue(const MCInst &MI, AArch64MCCodeEmitter::getLabelOpValue(const MCInst &MI,
unsigned OpIdx, unsigned OpIdx,
SmallVectorImpl<MCFixup> &Fixups) const { SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
const MCOperand &MO = MI.getOperand(OpIdx); const MCOperand &MO = MI.getOperand(OpIdx);
if (MO.isExpr()) if (MO.isExpr())
return getAddressWithFixup(MO, fixupDesired, Fixups); return getAddressWithFixup(MO, fixupDesired, Fixups, STI);
assert(MO.isImm()); assert(MO.isImm());
return MO.getImm(); return MO.getImm();
@ -384,7 +422,8 @@ AArch64MCCodeEmitter::getLabelOpValue(const MCInst &MI,
unsigned unsigned
AArch64MCCodeEmitter::getLoadLitLabelOpValue(const MCInst &MI, AArch64MCCodeEmitter::getLoadLitLabelOpValue(const MCInst &MI,
unsigned OpIdx, unsigned OpIdx,
SmallVectorImpl<MCFixup> &Fixups) const { SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
const MCOperand &MO = MI.getOperand(OpIdx); const MCOperand &MO = MI.getOperand(OpIdx);
if (MO.isImm()) if (MO.isImm())
@ -402,14 +441,15 @@ AArch64MCCodeEmitter::getLoadLitLabelOpValue(const MCInst &MI,
FixupKind = AArch64::fixup_a64_ld_prel; FixupKind = AArch64::fixup_a64_ld_prel;
} }
return getAddressWithFixup(MO, FixupKind, Fixups); return getAddressWithFixup(MO, FixupKind, Fixups, STI);
} }
unsigned unsigned
AArch64MCCodeEmitter::getMachineOpValue(const MCInst &MI, AArch64MCCodeEmitter::getMachineOpValue(const MCInst &MI,
const MCOperand &MO, const MCOperand &MO,
SmallVectorImpl<MCFixup> &Fixups) const { SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
if (MO.isReg()) { if (MO.isReg()) {
return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg()); return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg());
} else if (MO.isImm()) { } else if (MO.isImm()) {
@ -422,7 +462,8 @@ AArch64MCCodeEmitter::getMachineOpValue(const MCInst &MI,
unsigned unsigned
AArch64MCCodeEmitter::getMoveWideImmOpValue(const MCInst &MI, unsigned OpIdx, AArch64MCCodeEmitter::getMoveWideImmOpValue(const MCInst &MI, unsigned OpIdx,
SmallVectorImpl<MCFixup> &Fixups) const { SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
const MCOperand &UImm16MO = MI.getOperand(OpIdx); const MCOperand &UImm16MO = MI.getOperand(OpIdx);
const MCOperand &ShiftMO = MI.getOperand(OpIdx + 1); const MCOperand &ShiftMO = MI.getOperand(OpIdx + 1);
@ -483,12 +524,13 @@ AArch64MCCodeEmitter::getMoveWideImmOpValue(const MCInst &MI, unsigned OpIdx,
requestedFixup = AArch64::fixup_a64_movw_tprel_g0_nc; break; requestedFixup = AArch64::fixup_a64_movw_tprel_g0_nc; break;
} }
return Result | getAddressWithFixup(UImm16MO, requestedFixup, Fixups); return Result | getAddressWithFixup(UImm16MO, requestedFixup, Fixups, STI);
} }
template<int hasRs, int hasRt2> unsigned template<int hasRs, int hasRt2> unsigned
AArch64MCCodeEmitter::fixLoadStoreExclusive(const MCInst &MI, AArch64MCCodeEmitter::fixLoadStoreExclusive(const MCInst &MI,
unsigned EncodedValue) const { unsigned EncodedValue,
const MCSubtargetInfo &STI) const {
if (!hasRs) EncodedValue |= 0x001F0000; if (!hasRs) EncodedValue |= 0x001F0000;
if (!hasRt2) EncodedValue |= 0x00007C00; if (!hasRt2) EncodedValue |= 0x00007C00;
@ -496,7 +538,8 @@ AArch64MCCodeEmitter::fixLoadStoreExclusive(const MCInst &MI,
} }
unsigned unsigned
AArch64MCCodeEmitter::fixMOVZ(const MCInst &MI, unsigned EncodedValue) const { AArch64MCCodeEmitter::fixMOVZ(const MCInst &MI, unsigned EncodedValue,
const MCSubtargetInfo &STI) const {
// If one of the signed fixup kinds is applied to a MOVZ instruction, the // If one of the signed fixup kinds is applied to a MOVZ instruction, the
// eventual result could be either a MOVZ or a MOVN. It's the MCCodeEmitter's // eventual result could be either a MOVZ or a MOVN. It's the MCCodeEmitter's
// job to ensure that any bits possibly affected by this are 0. This means we // job to ensure that any bits possibly affected by this are 0. This means we
@ -530,7 +573,8 @@ AArch64MCCodeEmitter::fixMOVZ(const MCInst &MI, unsigned EncodedValue) const {
unsigned unsigned
AArch64MCCodeEmitter::fixMulHigh(const MCInst &MI, AArch64MCCodeEmitter::fixMulHigh(const MCInst &MI,
unsigned EncodedValue) const { unsigned EncodedValue,
const MCSubtargetInfo &STI) const {
// The Ra field of SMULH and UMULH is unused: it should be assembled as 31 // The Ra field of SMULH and UMULH is unused: it should be assembled as 31
// (i.e. all bits 1) but is ignored by the processor. // (i.e. all bits 1) but is ignored by the processor.
EncodedValue |= 0x1f << 10; EncodedValue |= 0x1f << 10;
@ -559,7 +603,7 @@ EncodeInstruction(const MCInst &MI, raw_ostream &OS,
return; return;
} }
uint32_t Binary = getBinaryCodeForInstr(MI, Fixups); uint32_t Binary = getBinaryCodeForInstr(MI, Fixups, STI);
EmitInstruction(Binary, OS); EmitInstruction(Binary, OS);
} }

386
lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
View File

@ -67,107 +67,131 @@ public:
// getBinaryCodeForInstr - TableGen'erated function for getting the // getBinaryCodeForInstr - TableGen'erated function for getting the
// binary encoding for an instruction. // binary encoding for an instruction.
uint64_t getBinaryCodeForInstr(const MCInst &MI, uint64_t getBinaryCodeForInstr(const MCInst &MI,
SmallVectorImpl<MCFixup> &Fixups) const; SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
/// getMachineOpValue - Return binary encoding of operand. If the machine /// getMachineOpValue - Return binary encoding of operand. If the machine
/// operand requires relocation, record the relocation and return zero. /// operand requires relocation, record the relocation and return zero.
unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO, unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO,
SmallVectorImpl<MCFixup> &Fixups) const; SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
/// getHiLo16ImmOpValue - Return the encoding for the hi / low 16-bit of /// getHiLo16ImmOpValue - Return the encoding for the hi / low 16-bit of
/// the specified operand. This is used for operands with :lower16: and /// the specified operand. This is used for operands with :lower16: and
/// :upper16: prefixes. /// :upper16: prefixes.
uint32_t getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx, uint32_t getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx,
SmallVectorImpl<MCFixup> &Fixups) const; SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
bool EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx, bool EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx,
unsigned &Reg, unsigned &Imm, unsigned &Reg, unsigned &Imm,
SmallVectorImpl<MCFixup> &Fixups) const; SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
/// getThumbBLTargetOpValue - Return encoding info for Thumb immediate /// getThumbBLTargetOpValue - Return encoding info for Thumb immediate
/// BL branch target. /// BL branch target.
uint32_t getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx, uint32_t getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
SmallVectorImpl<MCFixup> &Fixups) const; SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
/// getThumbBLXTargetOpValue - Return encoding info for Thumb immediate /// getThumbBLXTargetOpValue - Return encoding info for Thumb immediate
/// BLX branch target. /// BLX branch target.
uint32_t getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx, uint32_t getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
SmallVectorImpl<MCFixup> &Fixups) const; SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
/// getThumbBRTargetOpValue - Return encoding info for Thumb branch target. /// getThumbBRTargetOpValue - Return encoding info for Thumb branch target.
uint32_t getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx, uint32_t getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx,
SmallVectorImpl<MCFixup> &Fixups) const; SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
/// getThumbBCCTargetOpValue - Return encoding info for Thumb branch target. /// getThumbBCCTargetOpValue - Return encoding info for Thumb branch target.
uint32_t getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx, uint32_t getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx,
SmallVectorImpl<MCFixup> &Fixups) const; SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
/// getThumbCBTargetOpValue - Return encoding info for Thumb branch target. /// getThumbCBTargetOpValue - Return encoding info for Thumb branch target.
uint32_t getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx, uint32_t getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx,
SmallVectorImpl<MCFixup> &Fixups) const; SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
/// getBranchTargetOpValue - Return encoding info for 24-bit immediate /// getBranchTargetOpValue - Return encoding info for 24-bit immediate
/// branch target. /// branch target.
uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
SmallVectorImpl<MCFixup> &Fixups) const; SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
/// getUnconditionalBranchTargetOpValue - Return encoding info for 24-bit /// getUnconditionalBranchTargetOpValue - Return encoding info for 24-bit
/// immediate Thumb2 direct branch target. /// immediate Thumb2 direct branch target.
uint32_t getUnconditionalBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, uint32_t getUnconditionalBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
SmallVectorImpl<MCFixup> &Fixups) const; SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
/// getARMBranchTargetOpValue - Return encoding info for 24-bit immediate /// getARMBranchTargetOpValue - Return encoding info for 24-bit immediate
/// branch target. /// branch target.
uint32_t getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, uint32_t getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
SmallVectorImpl<MCFixup> &Fixups) const; SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
uint32_t getARMBLTargetOpValue(const MCInst &MI, unsigned OpIdx, uint32_t getARMBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
SmallVectorImpl<MCFixup> &Fixups) const; SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
uint32_t getARMBLXTargetOpValue(const MCInst &MI, unsigned OpIdx, uint32_t getARMBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
SmallVectorImpl<MCFixup> &Fixups) const; SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
/// getAdrLabelOpValue - Return encoding info for 12-bit immediate /// getAdrLabelOpValue - Return encoding info for 12-bit immediate
/// ADR label target. /// ADR label target.
uint32_t getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx, uint32_t getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
SmallVectorImpl<MCFixup> &Fixups) const; SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
uint32_t getThumbAdrLabelOpValue(const MCInst &MI, unsigned OpIdx, uint32_t getThumbAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
SmallVectorImpl<MCFixup> &Fixups) const; SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
uint32_t getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx, uint32_t getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
SmallVectorImpl<MCFixup> &Fixups) const; SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
/// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12' /// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12'
/// operand. /// operand.
uint32_t getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx, uint32_t getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
SmallVectorImpl<MCFixup> &Fixups) const; SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
/// getThumbAddrModeRegRegOpValue - Return encoding for 'reg + reg' operand. /// getThumbAddrModeRegRegOpValue - Return encoding for 'reg + reg' operand.
uint32_t getThumbAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx, uint32_t getThumbAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx,
SmallVectorImpl<MCFixup> &Fixups)const; SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
/// getT2AddrModeImm8s4OpValue - Return encoding info for 'reg +/- imm8<<2' /// getT2AddrModeImm8s4OpValue - Return encoding info for 'reg +/- imm8<<2'
/// operand. /// operand.
uint32_t getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx, uint32_t getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx,
SmallVectorImpl<MCFixup> &Fixups) const; SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
/// getT2AddrModeImm0_1020s4OpValue - Return encoding info for 'reg + imm8<<2' /// getT2AddrModeImm0_1020s4OpValue - Return encoding info for 'reg + imm8<<2'
/// operand. /// operand.
uint32_t getT2AddrModeImm0_1020s4OpValue(const MCInst &MI, unsigned OpIdx, uint32_t getT2AddrModeImm0_1020s4OpValue(const MCInst &MI, unsigned OpIdx,
SmallVectorImpl<MCFixup> &Fixups) const; SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
/// getT2Imm8s4OpValue - Return encoding info for '+/- imm8<<2' /// getT2Imm8s4OpValue - Return encoding info for '+/- imm8<<2'
/// operand. /// operand.
uint32_t getT2Imm8s4OpValue(const MCInst &MI, unsigned OpIdx, uint32_t getT2Imm8s4OpValue(const MCInst &MI, unsigned OpIdx,
SmallVectorImpl<MCFixup> &Fixups) const; SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
/// getLdStSORegOpValue - Return encoding info for 'reg +/- reg shop imm' /// getLdStSORegOpValue - Return encoding info for 'reg +/- reg shop imm'
/// operand as needed by load/store instructions. /// operand as needed by load/store instructions.
uint32_t getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx, uint32_t getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx,
SmallVectorImpl<MCFixup> &Fixups) const; SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
/// getLdStmModeOpValue - Return encoding for load/store multiple mode. /// getLdStmModeOpValue - Return encoding for load/store multiple mode.
uint32_t getLdStmModeOpValue(const MCInst &MI, unsigned OpIdx, uint32_t getLdStmModeOpValue(const MCInst &MI, unsigned OpIdx,
SmallVectorImpl<MCFixup> &Fixups) const { SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
ARM_AM::AMSubMode Mode = (ARM_AM::AMSubMode)MI.getOperand(OpIdx).getImm(); ARM_AM::AMSubMode Mode = (ARM_AM::AMSubMode)MI.getOperand(OpIdx).getImm();
switch (Mode) { switch (Mode) {
default: llvm_unreachable("Unknown addressing sub-mode!"); default: llvm_unreachable("Unknown addressing sub-mode!");
@ -193,44 +217,54 @@ public:
/// getAddrMode2OpValue - Return encoding for addrmode2 operands. /// getAddrMode2OpValue - Return encoding for addrmode2 operands.
uint32_t getAddrMode2OpValue(const MCInst &MI, unsigned OpIdx, uint32_t getAddrMode2OpValue(const MCInst &MI, unsigned OpIdx,
SmallVectorImpl<MCFixup> &Fixups) const; SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
/// getAddrMode2OffsetOpValue - Return encoding for am2offset operands. /// getAddrMode2OffsetOpValue - Return encoding for am2offset operands.
uint32_t getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx, uint32_t getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx,
SmallVectorImpl<MCFixup> &Fixups) const; SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
/// getPostIdxRegOpValue - Return encoding for postidx_reg operands. /// getPostIdxRegOpValue - Return encoding for postidx_reg operands.
uint32_t getPostIdxRegOpValue(const MCInst &MI, unsigned OpIdx, uint32_t getPostIdxRegOpValue(const MCInst &MI, unsigned OpIdx,
SmallVectorImpl<MCFixup> &Fixups) const; SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
/// getAddrMode3OffsetOpValue - Return encoding for am3offset operands. /// getAddrMode3OffsetOpValue - Return encoding for am3offset operands.
uint32_t getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx, uint32_t getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx,
SmallVectorImpl<MCFixup> &Fixups) const; SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
/// getAddrMode3OpValue - Return encoding for addrmode3 operands. /// getAddrMode3OpValue - Return encoding for addrmode3 operands.
uint32_t getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx, uint32_t getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx,
SmallVectorImpl<MCFixup> &Fixups) const; SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
/// getAddrModeThumbSPOpValue - Return encoding info for 'reg +/- imm12' /// getAddrModeThumbSPOpValue - Return encoding info for 'reg +/- imm12'
/// operand. /// operand.
uint32_t getAddrModeThumbSPOpValue(const MCInst &MI, unsigned OpIdx, uint32_t getAddrModeThumbSPOpValue(const MCInst &MI, unsigned OpIdx,
SmallVectorImpl<MCFixup> &Fixups) const; SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
/// getAddrModeISOpValue - Encode the t_addrmode_is# operands. /// getAddrModeISOpValue - Encode the t_addrmode_is# operands.
uint32_t getAddrModeISOpValue(const MCInst &MI, unsigned OpIdx, uint32_t getAddrModeISOpValue(const MCInst &MI, unsigned OpIdx,
SmallVectorImpl<MCFixup> &Fixups) const; SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
/// getAddrModePCOpValue - Return encoding for t_addrmode_pc operands. /// getAddrModePCOpValue - Return encoding for t_addrmode_pc operands.
uint32_t getAddrModePCOpValue(const MCInst &MI, unsigned OpIdx, uint32_t getAddrModePCOpValue(const MCInst &MI, unsigned OpIdx,
SmallVectorImpl<MCFixup> &Fixups) const; SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
/// getAddrMode5OpValue - Return encoding info for 'reg +/- imm8' operand. /// getAddrMode5OpValue - Return encoding info for 'reg +/- imm8' operand.
uint32_t getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx, uint32_t getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
SmallVectorImpl<MCFixup> &Fixups) const; SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
/// getCCOutOpValue - Return encoding of the 's' bit. /// getCCOutOpValue - Return encoding of the 's' bit.
unsigned getCCOutOpValue(const MCInst &MI, unsigned Op, unsigned getCCOutOpValue(const MCInst &MI, unsigned Op,
SmallVectorImpl<MCFixup> &Fixups) const { SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
// The operand is either reg0 or CPSR. The 's' bit is encoded as '0' or // The operand is either reg0 or CPSR. The 's' bit is encoded as '0' or
// '1' respectively. // '1' respectively.
return MI.getOperand(Op).getReg() == ARM::CPSR; return MI.getOperand(Op).getReg() == ARM::CPSR;
@ -238,7 +272,8 @@ public:
/// getSOImmOpValue - Return an encoded 12-bit shifted-immediate value. /// getSOImmOpValue - Return an encoded 12-bit shifted-immediate value.
unsigned getSOImmOpValue(const MCInst &MI, unsigned Op, unsigned getSOImmOpValue(const MCInst &MI, unsigned Op,
SmallVectorImpl<MCFixup> &Fixups) const { SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
unsigned SoImm = MI.getOperand(Op).getImm(); unsigned SoImm = MI.getOperand(Op).getImm();
int SoImmVal = ARM_AM::getSOImmVal(SoImm); int SoImmVal = ARM_AM::getSOImmVal(SoImm);
assert(SoImmVal != -1 && "Not a valid so_imm value!"); assert(SoImmVal != -1 && "Not a valid so_imm value!");
@ -254,7 +289,8 @@ public:
/// getT2SOImmOpValue - Return an encoded 12-bit shifted-immediate value. /// getT2SOImmOpValue - Return an encoded 12-bit shifted-immediate value.
unsigned getT2SOImmOpValue(const MCInst &MI, unsigned Op, unsigned getT2SOImmOpValue(const MCInst &MI, unsigned Op,
SmallVectorImpl<MCFixup> &Fixups) const { SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
unsigned SoImm = MI.getOperand(Op).getImm(); unsigned SoImm = MI.getOperand(Op).getImm();
unsigned Encoded = ARM_AM::getT2SOImmVal(SoImm); unsigned Encoded = ARM_AM::getT2SOImmVal(SoImm);
assert(Encoded != ~0U && "Not a Thumb2 so_imm value?"); assert(Encoded != ~0U && "Not a Thumb2 so_imm value?");
@ -262,64 +298,88 @@ public:
} }
unsigned getT2AddrModeSORegOpValue(const MCInst &MI, unsigned OpNum, unsigned getT2AddrModeSORegOpValue(const MCInst &MI, unsigned OpNum,
SmallVectorImpl<MCFixup> &Fixups) const; SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
unsigned getT2AddrModeImm8OpValue(const MCInst &MI, unsigned OpNum, unsigned getT2AddrModeImm8OpValue(const MCInst &MI, unsigned OpNum,
SmallVectorImpl<MCFixup> &Fixups) const; SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
unsigned getT2AddrModeImm8OffsetOpValue(const MCInst &MI, unsigned OpNum, unsigned getT2AddrModeImm8OffsetOpValue(const MCInst &MI, unsigned OpNum,
SmallVectorImpl<MCFixup> &Fixups) const; SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
unsigned getT2AddrModeImm12OffsetOpValue(const MCInst &MI, unsigned OpNum, unsigned getT2AddrModeImm12OffsetOpValue(const MCInst &MI, unsigned OpNum,
SmallVectorImpl<MCFixup> &Fixups) const; SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
/// getSORegOpValue - Return an encoded so_reg shifted register value. /// getSORegOpValue - Return an encoded so_reg shifted register value.
unsigned getSORegRegOpValue(const MCInst &MI, unsigned Op, unsigned getSORegRegOpValue(const MCInst &MI, unsigned Op,
SmallVectorImpl<MCFixup> &Fixups) const; SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
unsigned getSORegImmOpValue(const MCInst &MI, unsigned Op, unsigned getSORegImmOpValue(const MCInst &MI, unsigned Op,
SmallVectorImpl<MCFixup> &Fixups) const; SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
unsigned getT2SORegOpValue(const MCInst &MI, unsigned Op, unsigned getT2SORegOpValue(const MCInst &MI, unsigned Op,
SmallVectorImpl<MCFixup> &Fixups) const; SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
unsigned getNEONVcvtImm32OpValue(const MCInst &MI, unsigned Op, unsigned getNEONVcvtImm32OpValue(const MCInst &MI, unsigned Op,
SmallVectorImpl<MCFixup> &Fixups) const { SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
return 64 - MI.getOperand(Op).getImm(); return 64 - MI.getOperand(Op).getImm();
} }
unsigned getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op, unsigned getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op,
SmallVectorImpl<MCFixup> &Fixups) const; SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
unsigned getRegisterListOpValue(const MCInst &MI, unsigned Op, unsigned getRegisterListOpValue(const MCInst &MI, unsigned Op,
SmallVectorImpl<MCFixup> &Fixups) const; SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
unsigned getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op, unsigned getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op,
SmallVectorImpl<MCFixup> &Fixups) const; SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
unsigned getAddrMode6OneLane32AddressOpValue(const MCInst &MI, unsigned Op, unsigned getAddrMode6OneLane32AddressOpValue(const MCInst &MI, unsigned Op,
SmallVectorImpl<MCFixup> &Fixups) const; SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
unsigned getAddrMode6DupAddressOpValue(const MCInst &MI, unsigned Op, unsigned getAddrMode6DupAddressOpValue(const MCInst &MI, unsigned Op,
SmallVectorImpl<MCFixup> &Fixups) const; SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
unsigned getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op, unsigned getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op,
SmallVectorImpl<MCFixup> &Fixups) const; SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
unsigned getShiftRight8Imm(const MCInst &MI, unsigned Op, unsigned getShiftRight8Imm(const MCInst &MI, unsigned Op,
SmallVectorImpl<MCFixup> &Fixups) const; SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
unsigned getShiftRight16Imm(const MCInst &MI, unsigned Op, unsigned getShiftRight16Imm(const MCInst &MI, unsigned Op,
SmallVectorImpl<MCFixup> &Fixups) const; SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
unsigned getShiftRight32Imm(const MCInst &MI, unsigned Op, unsigned getShiftRight32Imm(const MCInst &MI, unsigned Op,
SmallVectorImpl<MCFixup> &Fixups) const; SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
unsigned getShiftRight64Imm(const MCInst &MI, unsigned Op, unsigned getShiftRight64Imm(const MCInst &MI, unsigned Op,
SmallVectorImpl<MCFixup> &Fixups) const; SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
unsigned getThumbSRImmOpValue(const MCInst &MI, unsigned Op, unsigned getThumbSRImmOpValue(const MCInst &MI, unsigned Op,
SmallVectorImpl<MCFixup> &Fixups) const; SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
unsigned NEONThumb2DataIPostEncoder(const MCInst &MI, unsigned NEONThumb2DataIPostEncoder(const MCInst &MI,
unsigned EncodedValue) const; unsigned EncodedValue,
const MCSubtargetInfo &STI) const;
unsigned NEONThumb2LoadStorePostEncoder(const MCInst &MI, unsigned NEONThumb2LoadStorePostEncoder(const MCInst &MI,
unsigned EncodedValue) const; unsigned EncodedValue,
const MCSubtargetInfo &STI) const;
unsigned NEONThumb2DupPostEncoder(const MCInst &MI, unsigned NEONThumb2DupPostEncoder(const MCInst &MI,
unsigned EncodedValue) const; unsigned EncodedValue,
const MCSubtargetInfo &STI) const;
unsigned NEONThumb2V8PostEncoder(const MCInst &MI, unsigned NEONThumb2V8PostEncoder(const MCInst &MI,
unsigned EncodedValue) const; unsigned EncodedValue,
const MCSubtargetInfo &STI) const;
unsigned VFPThumb2PostEncoder(const MCInst &MI, unsigned VFPThumb2PostEncoder(const MCInst &MI,
unsigned EncodedValue) const; unsigned EncodedValue,
const MCSubtargetInfo &STI) const;
void EmitByte(unsigned char C, raw_ostream &OS) const { void EmitByte(unsigned char C, raw_ostream &OS) const {
OS << (char)C; OS << (char)C;
@ -351,7 +411,8 @@ MCCodeEmitter *llvm::createARMMCCodeEmitter(const MCInstrInfo &MCII,
/// instructions, and rewrite them to their Thumb2 form if we are currently in /// instructions, and rewrite them to their Thumb2 form if we are currently in
/// Thumb2 mode. /// Thumb2 mode.
unsigned ARMMCCodeEmitter::NEONThumb2DataIPostEncoder(const MCInst &MI, unsigned ARMMCCodeEmitter::NEONThumb2DataIPostEncoder(const MCInst &MI,
unsigned EncodedValue) const { unsigned EncodedValue,
const MCSubtargetInfo &STI) const {
if (isThumb2()) { if (isThumb2()) {
// NEON Thumb2 data-processsing encodings are very simple: bit 24 is moved // NEON Thumb2 data-processsing encodings are very simple: bit 24 is moved
// to bit 12 of the high half-word (i.e. bit 28), and bits 27-24 are // to bit 12 of the high half-word (i.e. bit 28), and bits 27-24 are
@ -370,7 +431,8 @@ unsigned ARMMCCodeEmitter::NEONThumb2DataIPostEncoder(const MCInst &MI,
/// instructions, and rewrite them to their Thumb2 form if we are currently in /// instructions, and rewrite them to their Thumb2 form if we are currently in
/// Thumb2 mode. /// Thumb2 mode.
unsigned ARMMCCodeEmitter::NEONThumb2LoadStorePostEncoder(const MCInst &MI, unsigned ARMMCCodeEmitter::NEONThumb2LoadStorePostEncoder(const MCInst &MI,
unsigned EncodedValue) const { unsigned EncodedValue,
const MCSubtargetInfo &STI) const {
if (isThumb2()) { if (isThumb2()) {
EncodedValue &= 0xF0FFFFFF; EncodedValue &= 0xF0FFFFFF;
EncodedValue |= 0x09000000; EncodedValue |= 0x09000000;
@ -383,7 +445,8 @@ unsigned ARMMCCodeEmitter::NEONThumb2LoadStorePostEncoder(const MCInst &MI,
/// instructions, and rewrite them to their Thumb2 form if we are currently in /// instructions, and rewrite them to their Thumb2 form if we are currently in
/// Thumb2 mode. /// Thumb2 mode.
unsigned ARMMCCodeEmitter::NEONThumb2DupPostEncoder(const MCInst &MI, unsigned ARMMCCodeEmitter::NEONThumb2DupPostEncoder(const MCInst &MI,
unsigned EncodedValue) const { unsigned EncodedValue,
const MCSubtargetInfo &STI) const {
if (isThumb2()) { if (isThumb2()) {
EncodedValue &= 0x00FFFFFF; EncodedValue &= 0x00FFFFFF;
EncodedValue |= 0xEE000000; EncodedValue |= 0xEE000000;
@ -395,7 +458,8 @@ unsigned ARMMCCodeEmitter::NEONThumb2DupPostEncoder(const MCInst &MI,
/// Post-process encoded NEON v8 instructions, and rewrite them to Thumb2 form /// Post-process encoded NEON v8 instructions, and rewrite them to Thumb2 form
/// if we are in Thumb2. /// if we are in Thumb2.
unsigned ARMMCCodeEmitter::NEONThumb2V8PostEncoder(const MCInst &MI, unsigned ARMMCCodeEmitter::NEONThumb2V8PostEncoder(const MCInst &MI,
unsigned EncodedValue) const { unsigned EncodedValue,
const MCSubtargetInfo &STI) const {
if (isThumb2()) { if (isThumb2()) {
EncodedValue |= 0xC000000; // Set bits 27-26 EncodedValue |= 0xC000000; // Set bits 27-26
} }
@ -406,7 +470,8 @@ unsigned ARMMCCodeEmitter::NEONThumb2V8PostEncoder(const MCInst &MI,
/// VFPThumb2PostEncoder - Post-process encoded VFP instructions and rewrite /// VFPThumb2PostEncoder - Post-process encoded VFP instructions and rewrite
/// them to their Thumb2 form if we are currently in Thumb2 mode. /// them to their Thumb2 form if we are currently in Thumb2 mode.
unsigned ARMMCCodeEmitter:: unsigned ARMMCCodeEmitter::
VFPThumb2PostEncoder(const MCInst &MI, unsigned EncodedValue) const { VFPThumb2PostEncoder(const MCInst &MI, unsigned EncodedValue,
const MCSubtargetInfo &STI) const {
if (isThumb2()) { if (isThumb2()) {
EncodedValue &= 0x0FFFFFFF; EncodedValue &= 0x0FFFFFFF;
EncodedValue |= 0xE0000000; EncodedValue |= 0xE0000000;
@ -418,7 +483,8 @@ VFPThumb2PostEncoder(const MCInst &MI, unsigned EncodedValue) const {
/// operand requires relocation, record the relocation and return zero. /// operand requires relocation, record the relocation and return zero.
unsigned ARMMCCodeEmitter:: unsigned ARMMCCodeEmitter::
getMachineOpValue(const MCInst &MI, const MCOperand &MO, getMachineOpValue(const MCInst &MI, const MCOperand &MO,
SmallVectorImpl<MCFixup> &Fixups) const { SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
if (MO.isReg()) { if (MO.isReg()) {
unsigned Reg = MO.getReg(); unsigned Reg = MO.getReg();
unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg); unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg);
@ -446,7 +512,8 @@ getMachineOpValue(const MCInst &MI, const MCOperand &MO,
/// getAddrModeImmOpValue - Return encoding info for 'reg +/- imm' operand. /// getAddrModeImmOpValue - Return encoding info for 'reg +/- imm' operand.
bool ARMMCCodeEmitter:: bool ARMMCCodeEmitter::
EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx, unsigned &Reg, EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx, unsigned &Reg,
unsigned &Imm, SmallVectorImpl<MCFixup> &Fixups) const { unsigned &Imm, SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
const MCOperand &MO = MI.getOperand(OpIdx); const MCOperand &MO = MI.getOperand(OpIdx);
const MCOperand &MO1 = MI.getOperand(OpIdx + 1); const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
@ -475,7 +542,8 @@ EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx, unsigned &Reg,
/// which is either an immediate or requires a fixup. /// which is either an immediate or requires a fixup.
static uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, static uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
unsigned FixupKind, unsigned FixupKind,
SmallVectorImpl<MCFixup> &Fixups) { SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) {
const MCOperand &MO = MI.getOperand(OpIdx); const MCOperand &MO = MI.getOperand(OpIdx);
// If the destination is an immediate, we have nothing to do. // If the destination is an immediate, we have nothing to do.
@ -511,11 +579,12 @@ static int32_t encodeThumbBLOffset(int32_t offset) {
/// getThumbBLTargetOpValue - Return encoding info for immediate branch target. /// getThumbBLTargetOpValue - Return encoding info for immediate branch target.
uint32_t ARMMCCodeEmitter:: uint32_t ARMMCCodeEmitter::
getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx, getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
SmallVectorImpl<MCFixup> &Fixups) const { SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
const MCOperand MO = MI.getOperand(OpIdx); const MCOperand MO = MI.getOperand(OpIdx);
if (MO.isExpr()) if (MO.isExpr())
return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_bl, return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_bl,
Fixups); Fixups, STI);
return encodeThumbBLOffset(MO.getImm()); return encodeThumbBLOffset(MO.getImm());
} }
@ -523,43 +592,47 @@ getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
/// BLX branch target. /// BLX branch target.
uint32_t ARMMCCodeEmitter:: uint32_t ARMMCCodeEmitter::
getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx, getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
SmallVectorImpl<MCFixup> &Fixups) const { SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
const MCOperand MO = MI.getOperand(OpIdx); const MCOperand MO = MI.getOperand(OpIdx);
if (MO.isExpr()) if (MO.isExpr())
return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_blx, return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_blx,
Fixups); Fixups, STI);
return encodeThumbBLOffset(MO.getImm()); return encodeThumbBLOffset(MO.getImm());
} }
/// getThumbBRTargetOpValue - Return encoding info for Thumb branch target. /// getThumbBRTargetOpValue - Return encoding info for Thumb branch target.
uint32_t ARMMCCodeEmitter:: uint32_t ARMMCCodeEmitter::
getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx, getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx,
SmallVectorImpl<MCFixup> &Fixups) const { SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
const MCOperand MO = MI.getOperand(OpIdx); const MCOperand MO = MI.getOperand(OpIdx);
if (MO.isExpr()) if (MO.isExpr())
return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_br, return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_br,
Fixups); Fixups, STI);
return (MO.getImm() >> 1); return (MO.getImm() >> 1);
} }
/// getThumbBCCTargetOpValue - Return encoding info for Thumb branch target. /// getThumbBCCTargetOpValue - Return encoding info for Thumb branch target.
uint32_t ARMMCCodeEmitter:: uint32_t ARMMCCodeEmitter::
getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx, getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx,
SmallVectorImpl<MCFixup> &Fixups) const { SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
const MCOperand MO = MI.getOperand(OpIdx); const MCOperand MO = MI.getOperand(OpIdx);
if (MO.isExpr()) if (MO.isExpr())
return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_bcc, return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_bcc,
Fixups); Fixups, STI);
return (MO.getImm() >> 1); return (MO.getImm() >> 1);
} }
/// getThumbCBTargetOpValue - Return encoding info for Thumb branch target. /// getThumbCBTargetOpValue - Return encoding info for Thumb branch target.
uint32_t ARMMCCodeEmitter:: uint32_t ARMMCCodeEmitter::
getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx, getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx,
SmallVectorImpl<MCFixup> &Fixups) const { SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
const MCOperand MO = MI.getOperand(OpIdx); const MCOperand MO = MI.getOperand(OpIdx);
if (MO.isExpr()) if (MO.isExpr())
return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_cb, Fixups); return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_cb, Fixups, STI);
return (MO.getImm() >> 1); return (MO.getImm() >> 1);
} }
@ -584,27 +657,29 @@ static bool HasConditionalBranch(const MCInst &MI) {
/// target. /// target.
uint32_t ARMMCCodeEmitter:: uint32_t ARMMCCodeEmitter::
getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
SmallVectorImpl<MCFixup> &Fixups) const { SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
// FIXME: This really, really shouldn't use TargetMachine. We don't want // FIXME: This really, really shouldn't use TargetMachine. We don't want
// coupling between MC and TM anywhere we can help it. // coupling between MC and TM anywhere we can help it.
if (isThumb2()) if (isThumb2())
return return
::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_condbranch, Fixups); ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_condbranch, Fixups, STI);
return getARMBranchTargetOpValue(MI, OpIdx, Fixups); return getARMBranchTargetOpValue(MI, OpIdx, Fixups, STI);
} }
/// getBranchTargetOpValue - Return encoding info for 24-bit immediate branch /// getBranchTargetOpValue - Return encoding info for 24-bit immediate branch
/// target. /// target.
uint32_t ARMMCCodeEmitter:: uint32_t ARMMCCodeEmitter::
getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
SmallVectorImpl<MCFixup> &Fixups) const { SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
const MCOperand MO = MI.getOperand(OpIdx); const MCOperand MO = MI.getOperand(OpIdx);
if (MO.isExpr()) { if (MO.isExpr()) {
if (HasConditionalBranch(MI)) if (HasConditionalBranch(MI))
return ::getBranchTargetOpValue(MI, OpIdx, return ::getBranchTargetOpValue(MI, OpIdx,
ARM::fixup_arm_condbranch, Fixups); ARM::fixup_arm_condbranch, Fixups, STI);
return ::getBranchTargetOpValue(MI, OpIdx, return ::getBranchTargetOpValue(MI, OpIdx,
ARM::fixup_arm_uncondbranch, Fixups); ARM::fixup_arm_uncondbranch, Fixups, STI);
} }
return MO.getImm() >> 2; return MO.getImm() >> 2;
@ -612,13 +687,14 @@ getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
uint32_t ARMMCCodeEmitter:: uint32_t ARMMCCodeEmitter::
getARMBLTargetOpValue(const MCInst &MI, unsigned OpIdx, getARMBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
SmallVectorImpl<MCFixup> &Fixups) const { SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
const MCOperand MO = MI.getOperand(OpIdx); const MCOperand MO = MI.getOperand(OpIdx);
if (MO.isExpr()) { if (MO.isExpr()) {
if (HasConditionalBranch(MI)) if (HasConditionalBranch(MI))
return ::getBranchTargetOpValue(MI, OpIdx, return ::getBranchTargetOpValue(MI, OpIdx,
ARM::fixup_arm_condbl, Fixups); ARM::fixup_arm_condbl, Fixups, STI);
return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_uncondbl, Fixups); return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_uncondbl, Fixups, STI);
} }
return MO.getImm() >> 2; return MO.getImm() >> 2;
@ -626,10 +702,11 @@ getARMBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
uint32_t ARMMCCodeEmitter:: uint32_t ARMMCCodeEmitter::
getARMBLXTargetOpValue(const MCInst &MI, unsigned OpIdx, getARMBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
SmallVectorImpl<MCFixup> &Fixups) const { SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
const MCOperand MO = MI.getOperand(OpIdx); const MCOperand MO = MI.getOperand(OpIdx);
if (MO.isExpr()) if (MO.isExpr())
return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_blx, Fixups); return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_blx, Fixups, STI);
return MO.getImm() >> 1; return MO.getImm() >> 1;
} }
@ -638,12 +715,13 @@ getARMBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
/// immediate branch target. /// immediate branch target.
uint32_t ARMMCCodeEmitter:: uint32_t ARMMCCodeEmitter::
getUnconditionalBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, getUnconditionalBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
SmallVectorImpl<MCFixup> &Fixups) const { SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
unsigned Val = 0; unsigned Val = 0;
const MCOperand MO = MI.getOperand(OpIdx); const MCOperand MO = MI.getOperand(OpIdx);
if(MO.isExpr()) if(MO.isExpr())
return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_uncondbranch, Fixups); return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_uncondbranch, Fixups, STI);
else else
Val = MO.getImm() >> 1; Val = MO.getImm() >> 1;
@ -667,11 +745,12 @@ getUnconditionalBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
/// ADR label target. /// ADR label target.
uint32_t ARMMCCodeEmitter:: uint32_t ARMMCCodeEmitter::
getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx, getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
SmallVectorImpl<MCFixup> &Fixups) const { SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
const MCOperand MO = MI.getOperand(OpIdx); const MCOperand MO = MI.getOperand(OpIdx);
if (MO.isExpr()) if (MO.isExpr())
return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_adr_pcrel_12, return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_adr_pcrel_12,
Fixups); Fixups, STI);
int64_t offset = MO.getImm(); int64_t offset = MO.getImm();
uint32_t Val = 0x2000; uint32_t Val = 0x2000;
@ -707,11 +786,12 @@ getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
/// target. /// target.
uint32_t ARMMCCodeEmitter:: uint32_t ARMMCCodeEmitter::
getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx, getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
SmallVectorImpl<MCFixup> &Fixups) const { SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
const MCOperand MO = MI.getOperand(OpIdx); const MCOperand MO = MI.getOperand(OpIdx);
if (MO.isExpr()) if (MO.isExpr())
return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_adr_pcrel_12, return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_adr_pcrel_12,
Fixups); Fixups, STI);
int32_t Val = MO.getImm(); int32_t Val = MO.getImm();
if (Val == INT32_MIN) if (Val == INT32_MIN)
Val = 0x1000; Val = 0x1000;
@ -726,11 +806,12 @@ getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
/// target. /// target.
uint32_t ARMMCCodeEmitter:: uint32_t ARMMCCodeEmitter::
getThumbAdrLabelOpValue(const MCInst &MI, unsigned OpIdx, getThumbAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
SmallVectorImpl<MCFixup> &Fixups) const { SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
const MCOperand MO = MI.getOperand(OpIdx); const MCOperand MO = MI.getOperand(OpIdx);
if (MO.isExpr()) if (MO.isExpr())
return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_thumb_adr_pcrel_10, return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_thumb_adr_pcrel_10,
Fixups); Fixups, STI);
return MO.getImm(); return MO.getImm();
} }
@ -738,7 +819,8 @@ getThumbAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
/// operand. /// operand.
uint32_t ARMMCCodeEmitter:: uint32_t ARMMCCodeEmitter::
getThumbAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx, getThumbAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx,
SmallVectorImpl<MCFixup> &) const { SmallVectorImpl<MCFixup> &,
const MCSubtargetInfo &STI) const {
// [Rn, Rm] // [Rn, Rm]
// {5-3} = Rm // {5-3} = Rm
// {2-0} = Rn // {2-0} = Rn
@ -752,7 +834,8 @@ getThumbAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx,
/// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12' operand. /// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12' operand.
uint32_t ARMMCCodeEmitter:: uint32_t ARMMCCodeEmitter::
getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx, getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
SmallVectorImpl<MCFixup> &Fixups) const { SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
// {17-13} = reg // {17-13} = reg
// {12} = (U)nsigned (add == '1', sub == '0') // {12} = (U)nsigned (add == '1', sub == '0')
// {11-0} = imm12 // {11-0} = imm12
@ -789,7 +872,7 @@ getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
Imm12 = Offset; Imm12 = Offset;
} }
} else } else
isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm12, Fixups); isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm12, Fixups, STI);
uint32_t Binary = Imm12 & 0xfff; uint32_t Binary = Imm12 & 0xfff;
// Immediate is always encoded as positive. The 'U' bit controls add vs sub. // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
@ -803,7 +886,8 @@ getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
/// '+/- imm8<<2' operand. /// '+/- imm8<<2' operand.
uint32_t ARMMCCodeEmitter:: uint32_t ARMMCCodeEmitter::
getT2Imm8s4OpValue(const MCInst &MI, unsigned OpIdx, getT2Imm8s4OpValue(const MCInst &MI, unsigned OpIdx,
SmallVectorImpl<MCFixup> &Fixups) const { SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
// FIXME: The immediate operand should have already been encoded like this // FIXME: The immediate operand should have already been encoded like this
// before ever getting here. The encoder method should just need to combine // before ever getting here. The encoder method should just need to combine
// the MI operands for the register and the offset into a single // the MI operands for the register and the offset into a single
@ -834,7 +918,8 @@ getT2Imm8s4OpValue(const MCInst &MI, unsigned OpIdx,
/// 'reg +/- imm8<<2' operand. /// 'reg +/- imm8<<2' operand.
uint32_t ARMMCCodeEmitter:: uint32_t ARMMCCodeEmitter::
getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx, getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx,
SmallVectorImpl<MCFixup> &Fixups) const { SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
// {12-9} = reg // {12-9} = reg
// {8} = (U)nsigned (add == '1', sub == '0') // {8} = (U)nsigned (add == '1', sub == '0')
// {7-0} = imm8 // {7-0} = imm8
@ -854,7 +939,7 @@ getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx,
++MCNumCPRelocations; ++MCNumCPRelocations;
} else } else
isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups); isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups, STI);
// FIXME: The immediate operand should have already been encoded like this // FIXME: The immediate operand should have already been encoded like this
// before ever getting here. The encoder method should just need to combine // before ever getting here. The encoder method should just need to combine
@ -874,7 +959,8 @@ getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx,
/// 'reg + imm8<<2' operand. /// 'reg + imm8<<2' operand.
uint32_t ARMMCCodeEmitter:: uint32_t ARMMCCodeEmitter::
getT2AddrModeImm0_1020s4OpValue(const MCInst &MI, unsigned OpIdx, getT2AddrModeImm0_1020s4OpValue(const MCInst &MI, unsigned OpIdx,
SmallVectorImpl<MCFixup> &Fixups) const { SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
// {11-8} = reg // {11-8} = reg
// {7-0} = imm8 // {7-0} = imm8
const MCOperand &MO = MI.getOperand(OpIdx); const MCOperand &MO = MI.getOperand(OpIdx);
@ -899,7 +985,8 @@ static bool EvaluateAsPCRel(const MCExpr *Expr) {
uint32_t uint32_t
ARMMCCodeEmitter::getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx, ARMMCCodeEmitter::getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx,
SmallVectorImpl<MCFixup> &Fixups) const { SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
// {20-16} = imm{15-12} // {20-16} = imm{15-12}
// {11-0} = imm{11-0} // {11-0} = imm{11-0}
const MCOperand &MO = MI.getOperand(OpIdx); const MCOperand &MO = MI.getOperand(OpIdx);
@ -972,7 +1059,8 @@ ARMMCCodeEmitter::getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx,
uint32_t ARMMCCodeEmitter:: uint32_t ARMMCCodeEmitter::
getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx, getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx,
SmallVectorImpl<MCFixup> &Fixups) const { SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
const MCOperand &MO = MI.getOperand(OpIdx); const MCOperand &MO = MI.getOperand(OpIdx);
const MCOperand &MO1 = MI.getOperand(OpIdx+1); const MCOperand &MO1 = MI.getOperand(OpIdx+1);
const MCOperand &MO2 = MI.getOperand(OpIdx+2); const MCOperand &MO2 = MI.getOperand(OpIdx+2);
@ -1005,21 +1093,23 @@ getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx,
uint32_t ARMMCCodeEmitter:: uint32_t ARMMCCodeEmitter::
getAddrMode2OpValue(const MCInst &MI, unsigned OpIdx, getAddrMode2OpValue(const MCInst &MI, unsigned OpIdx,
SmallVectorImpl<MCFixup> &Fixups) const { SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
// {17-14} Rn // {17-14} Rn
// {13} 1 == imm12, 0 == Rm // {13} 1 == imm12, 0 == Rm
// {12} isAdd // {12} isAdd
// {11-0} imm12/Rm // {11-0} imm12/Rm
const MCOperand &MO = MI.getOperand(OpIdx); const MCOperand &MO = MI.getOperand(OpIdx);
unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
uint32_t Binary = getAddrMode2OffsetOpValue(MI, OpIdx + 1, Fixups); uint32_t Binary = getAddrMode2OffsetOpValue(MI, OpIdx + 1, Fixups, STI);
Binary |= Rn << 14; Binary |= Rn << 14;
return Binary; return Binary;
} }
uint32_t ARMMCCodeEmitter:: uint32_t ARMMCCodeEmitter::
getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx, getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx,
SmallVectorImpl<MCFixup> &Fixups) const { SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
// {13} 1 == imm12, 0 == Rm // {13} 1 == imm12, 0 == Rm
// {12} isAdd // {12} isAdd
// {11-0} imm12/Rm // {11-0} imm12/Rm
@ -1041,7 +1131,8 @@ getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx,
uint32_t ARMMCCodeEmitter:: uint32_t ARMMCCodeEmitter::
getPostIdxRegOpValue(const MCInst &MI, unsigned OpIdx, getPostIdxRegOpValue(const MCInst &MI, unsigned OpIdx,
SmallVectorImpl<MCFixup> &Fixups) const { SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
// {4} isAdd // {4} isAdd
// {3-0} Rm // {3-0} Rm
const MCOperand &MO = MI.getOperand(OpIdx); const MCOperand &MO = MI.getOperand(OpIdx);
@ -1052,7 +1143,8 @@ getPostIdxRegOpValue(const MCInst &MI, unsigned OpIdx,
uint32_t ARMMCCodeEmitter:: uint32_t ARMMCCodeEmitter::
getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx, getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx,
SmallVectorImpl<MCFixup> &Fixups) const { SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
// {9} 1 == imm8, 0 == Rm // {9} 1 == imm8, 0 == Rm
// {8} isAdd // {8} isAdd
// {7-4} imm7_4/zero // {7-4} imm7_4/zero
@ -1071,7 +1163,8 @@ getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx,
uint32_t ARMMCCodeEmitter:: uint32_t ARMMCCodeEmitter::
getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx, getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx,
SmallVectorImpl<MCFixup> &Fixups) const { SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
// {13} 1 == imm8, 0 == Rm // {13} 1 == imm8, 0 == Rm
// {12-9} Rn // {12-9} Rn
// {8} isAdd // {8} isAdd
@ -1107,7 +1200,8 @@ getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx,
/// getAddrModeThumbSPOpValue - Encode the t_addrmode_sp operands. /// getAddrModeThumbSPOpValue - Encode the t_addrmode_sp operands.
uint32_t ARMMCCodeEmitter:: uint32_t ARMMCCodeEmitter::
getAddrModeThumbSPOpValue(const MCInst &MI, unsigned OpIdx, getAddrModeThumbSPOpValue(const MCInst &MI, unsigned OpIdx,
SmallVectorImpl<MCFixup> &Fixups) const { SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
// [SP, #imm] // [SP, #imm]
// {7-0} = imm8 // {7-0} = imm8
const MCOperand &MO1 = MI.getOperand(OpIdx + 1); const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
@ -1122,7 +1216,8 @@ getAddrModeThumbSPOpValue(const MCInst &MI, unsigned OpIdx,
/// getAddrModeISOpValue - Encode the t_addrmode_is# operands. /// getAddrModeISOpValue - Encode the t_addrmode_is# operands.
uint32_t ARMMCCodeEmitter:: uint32_t ARMMCCodeEmitter::
getAddrModeISOpValue(const MCInst &MI, unsigned OpIdx, getAddrModeISOpValue(const MCInst &MI, unsigned OpIdx,
SmallVectorImpl<MCFixup> &Fixups) const { SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
// [Rn, #imm] // [Rn, #imm]
// {7-3} = imm5 // {7-3} = imm5
// {2-0} = Rn // {2-0} = Rn
@ -1136,17 +1231,19 @@ getAddrModeISOpValue(const MCInst &MI, unsigned OpIdx,
/// getAddrModePCOpValue - Return encoding for t_addrmode_pc operands. /// getAddrModePCOpValue - Return encoding for t_addrmode_pc operands.
uint32_t ARMMCCodeEmitter:: uint32_t ARMMCCodeEmitter::
getAddrModePCOpValue(const MCInst &MI, unsigned OpIdx, getAddrModePCOpValue(const MCInst &MI, unsigned OpIdx,
SmallVectorImpl<MCFixup> &Fixups) const { SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
const MCOperand MO = MI.getOperand(OpIdx); const MCOperand MO = MI.getOperand(OpIdx);
if (MO.isExpr()) if (MO.isExpr())
return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_cp, Fixups); return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_cp, Fixups, STI);
return (MO.getImm() >> 2); return (MO.getImm() >> 2);
} }
/// getAddrMode5OpValue - Return encoding info for 'reg +/- imm10' operand. /// getAddrMode5OpValue - Return encoding info for 'reg +/- imm10' operand.
uint32_t ARMMCCodeEmitter:: uint32_t ARMMCCodeEmitter::
getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx, getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
SmallVectorImpl<MCFixup> &Fixups) const { SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
// {12-9} = reg // {12-9} = reg
// {8} = (U)nsigned (add == '1', sub == '0') // {8} = (U)nsigned (add == '1', sub == '0')
// {7-0} = imm8 // {7-0} = imm8
@ -1170,7 +1267,7 @@ getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
++MCNumCPRelocations; ++MCNumCPRelocations;
} else { } else {
EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups); EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups, STI);
isAdd = ARM_AM::getAM5Op(Imm8) == ARM_AM::add; isAdd = ARM_AM::getAM5Op(Imm8) == ARM_AM::add;
} }
@ -1184,7 +1281,8 @@ getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
unsigned ARMMCCodeEmitter:: unsigned ARMMCCodeEmitter::
getSORegRegOpValue(const MCInst &MI, unsigned OpIdx, getSORegRegOpValue(const MCInst &MI, unsigned OpIdx,
SmallVectorImpl<MCFixup> &Fixups) const { SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
// Sub-operands are [reg, reg, imm]. The first register is Rm, the reg to be // Sub-operands are [reg, reg, imm]. The first register is Rm, the reg to be
// shifted. The second is Rs, the amount to shift by, and the third specifies // shifted. The second is Rs, the amount to shift by, and the third specifies
// the type of the shift. // the type of the shift.
@ -1231,7 +1329,8 @@ getSORegRegOpValue(const MCInst &MI, unsigned OpIdx,
unsigned ARMMCCodeEmitter:: unsigned ARMMCCodeEmitter::
getSORegImmOpValue(const MCInst &MI, unsigned OpIdx, getSORegImmOpValue(const MCInst &MI, unsigned OpIdx,
SmallVectorImpl<MCFixup> &Fixups) const { SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
// Sub-operands are [reg, imm]. The first register is Rm, the reg to be // Sub-operands are [reg, imm]. The first register is Rm, the reg to be
// shifted. The second is the amount to shift by. // shifted. The second is the amount to shift by.
// //
@ -1277,7 +1376,8 @@ getSORegImmOpValue(const MCInst &MI, unsigned OpIdx,
unsigned ARMMCCodeEmitter:: unsigned ARMMCCodeEmitter::
getT2AddrModeSORegOpValue(const MCInst &MI, unsigned OpNum, getT2AddrModeSORegOpValue(const MCInst &MI, unsigned OpNum,
SmallVectorImpl<MCFixup> &Fixups) const { SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
const MCOperand &MO1 = MI.getOperand(OpNum); const MCOperand &MO1 = MI.getOperand(OpNum);
const MCOperand &MO2 = MI.getOperand(OpNum+1); const MCOperand &MO2 = MI.getOperand(OpNum+1);
const MCOperand &MO3 = MI.getOperand(OpNum+2); const MCOperand &MO3 = MI.getOperand(OpNum+2);
@ -1295,7 +1395,8 @@ getT2AddrModeSORegOpValue(const MCInst &MI, unsigned OpNum,
unsigned ARMMCCodeEmitter:: unsigned ARMMCCodeEmitter::
getT2AddrModeImm8OpValue(const MCInst &MI, unsigned OpNum, getT2AddrModeImm8OpValue(const MCInst &MI, unsigned OpNum,
SmallVectorImpl<MCFixup> &Fixups) const { SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
const MCOperand &MO1 = MI.getOperand(OpNum); const MCOperand &MO1 = MI.getOperand(OpNum);
const MCOperand &MO2 = MI.getOperand(OpNum+1); const MCOperand &MO2 = MI.getOperand(OpNum+1);
@ -1316,7 +1417,8 @@ getT2AddrModeImm8OpValue(const MCInst &MI, unsigned OpNum,
unsigned ARMMCCodeEmitter:: unsigned ARMMCCodeEmitter::
getT2AddrModeImm8OffsetOpValue(const MCInst &MI, unsigned OpNum, getT2AddrModeImm8OffsetOpValue(const MCInst &MI, unsigned OpNum,
SmallVectorImpl<MCFixup> &Fixups) const { SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
const MCOperand &MO1 = MI.getOperand(OpNum); const MCOperand &MO1 = MI.getOperand(OpNum);
// FIXME: Needs fixup support. // FIXME: Needs fixup support.
@ -1332,7 +1434,8 @@ getT2AddrModeImm8OffsetOpValue(const MCInst &MI, unsigned OpNum,
unsigned ARMMCCodeEmitter:: unsigned ARMMCCodeEmitter::
getT2AddrModeImm12OffsetOpValue(const MCInst &MI, unsigned OpNum, getT2AddrModeImm12OffsetOpValue(const MCInst &MI, unsigned OpNum,
SmallVectorImpl<MCFixup> &Fixups) const { SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
const MCOperand &MO1 = MI.getOperand(OpNum); const MCOperand &MO1 = MI.getOperand(OpNum);
// FIXME: Needs fixup support. // FIXME: Needs fixup support.
@ -1348,7 +1451,8 @@ getT2AddrModeImm12OffsetOpValue(const MCInst &MI, unsigned OpNum,
unsigned ARMMCCodeEmitter:: unsigned ARMMCCodeEmitter::
getT2SORegOpValue(const MCInst &MI, unsigned OpIdx, getT2SORegOpValue(const MCInst &MI, unsigned OpIdx,
SmallVectorImpl<MCFixup> &Fixups) const { SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
// Sub-operands are [reg, imm]. The first register is Rm, the reg to be // Sub-operands are [reg, imm]. The first register is Rm, the reg to be
// shifted. The second is the amount to shift by. // shifted. The second is the amount to shift by.
// //
@ -1390,7 +1494,8 @@ getT2SORegOpValue(const MCInst &MI, unsigned OpIdx,
unsigned ARMMCCodeEmitter:: unsigned ARMMCCodeEmitter::
getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op, getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op,
SmallVectorImpl<MCFixup> &Fixups) const { SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
// 10 bits. lower 5 bits are are the lsb of the mask, high five bits are the // 10 bits. lower 5 bits are are the lsb of the mask, high five bits are the
// msb of the mask. // msb of the mask.
const MCOperand &MO = MI.getOperand(Op); const MCOperand &MO = MI.getOperand(Op);
@ -1403,7 +1508,8 @@ getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op,
unsigned ARMMCCodeEmitter:: unsigned ARMMCCodeEmitter::
getRegisterListOpValue(const MCInst &MI, unsigned Op, getRegisterListOpValue(const MCInst &MI, unsigned Op,
SmallVectorImpl<MCFixup> &Fixups) const { SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
// VLDM/VSTM: // VLDM/VSTM:
// {12-8} = Vd // {12-8} = Vd
// {7-0} = Number of registers // {7-0} = Number of registers
@ -1439,7 +1545,8 @@ getRegisterListOpValue(const MCInst &MI, unsigned Op,
/// with the alignment operand. /// with the alignment operand.
unsigned ARMMCCodeEmitter:: unsigned ARMMCCodeEmitter::
getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op, getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op,
SmallVectorImpl<MCFixup> &Fixups) const { SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
const MCOperand &Reg = MI.getOperand(Op); const MCOperand &Reg = MI.getOperand(Op);
const MCOperand &Imm = MI.getOperand(Op + 1); const MCOperand &Imm = MI.getOperand(Op + 1);
@ -1462,7 +1569,8 @@ getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op,
/// along with the alignment operand for use in VST1 and VLD1 with size 32. /// along with the alignment operand for use in VST1 and VLD1 with size 32.
unsigned ARMMCCodeEmitter:: unsigned ARMMCCodeEmitter::
getAddrMode6OneLane32AddressOpValue(const MCInst &MI, unsigned Op, getAddrMode6OneLane32AddressOpValue(const MCInst &MI, unsigned Op,
SmallVectorImpl<MCFixup> &Fixups) const { SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
const MCOperand &Reg = MI.getOperand(Op); const MCOperand &Reg = MI.getOperand(Op);
const MCOperand &Imm = MI.getOperand(Op + 1); const MCOperand &Imm = MI.getOperand(Op + 1);
@ -1488,7 +1596,8 @@ getAddrMode6OneLane32AddressOpValue(const MCInst &MI, unsigned Op,
/// different for VLD4-dup. /// different for VLD4-dup.
unsigned ARMMCCodeEmitter:: unsigned ARMMCCodeEmitter::
getAddrMode6DupAddressOpValue(const MCInst &MI, unsigned Op, getAddrMode6DupAddressOpValue(const MCInst &MI, unsigned Op,
SmallVectorImpl<MCFixup> &Fixups) const { SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
const MCOperand &Reg = MI.getOperand(Op); const MCOperand &Reg = MI.getOperand(Op);
const MCOperand &Imm = MI.getOperand(Op + 1); const MCOperand &Imm = MI.getOperand(Op + 1);
@ -1508,7 +1617,8 @@ getAddrMode6DupAddressOpValue(const MCInst &MI, unsigned Op,
unsigned ARMMCCodeEmitter:: unsigned ARMMCCodeEmitter::
getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op, getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op,
SmallVectorImpl<MCFixup> &Fixups) const { SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
const MCOperand &MO = MI.getOperand(Op); const MCOperand &MO = MI.getOperand(Op);
if (MO.getReg() == 0) return 0x0D; if (MO.getReg() == 0) return 0x0D;
return CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); return CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
@ -1516,25 +1626,29 @@ getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op,
unsigned ARMMCCodeEmitter:: unsigned ARMMCCodeEmitter::
getShiftRight8Imm(const MCInst &MI, unsigned Op, getShiftRight8Imm(const MCInst &MI, unsigned Op,
SmallVectorImpl<MCFixup> &Fixups) const { SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
return 8 - MI.getOperand(Op).getImm(); return 8 - MI.getOperand(Op).getImm();
} }
unsigned ARMMCCodeEmitter:: unsigned ARMMCCodeEmitter::
getShiftRight16Imm(const MCInst &MI, unsigned Op, getShiftRight16Imm(const MCInst &MI, unsigned Op,
SmallVectorImpl<MCFixup> &Fixups) const { SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
return 16 - MI.getOperand(Op).getImm(); return 16 - MI.getOperand(Op).getImm();
} }
unsigned ARMMCCodeEmitter:: unsigned ARMMCCodeEmitter::
getShiftRight32Imm(const MCInst &MI, unsigned Op, getShiftRight32Imm(const MCInst &MI, unsigned Op,
SmallVectorImpl<MCFixup> &Fixups) const { SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
return 32 - MI.getOperand(Op).getImm(); return 32 - MI.getOperand(Op).getImm();
} }
unsigned ARMMCCodeEmitter:: unsigned ARMMCCodeEmitter::
getShiftRight64Imm(const MCInst &MI, unsigned Op, getShiftRight64Imm(const MCInst &MI, unsigned Op,
SmallVectorImpl<MCFixup> &Fixups) const { SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
return 64 - MI.getOperand(Op).getImm(); return 64 - MI.getOperand(Op).getImm();
} }
@ -1554,7 +1668,7 @@ EncodeInstruction(const MCInst &MI, raw_ostream &OS,
else else
llvm_unreachable("Unexpected instruction size!"); llvm_unreachable("Unexpected instruction size!");
uint32_t Binary = getBinaryCodeForInstr(MI, Fixups); uint32_t Binary = getBinaryCodeForInstr(MI, Fixups, STI);
// Thumb 32-bit wide instructions need to emit the high order halfword // Thumb 32-bit wide instructions need to emit the high order halfword
// first. // first.
if (isThumb() && Size == 4) { if (isThumb() && Size == 4) {

105
lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
View File

@ -77,55 +77,68 @@ public:
// getBinaryCodeForInstr - TableGen'erated function for getting the // getBinaryCodeForInstr - TableGen'erated function for getting the
// binary encoding for an instruction. // binary encoding for an instruction.
uint64_t getBinaryCodeForInstr(const MCInst &MI, uint64_t getBinaryCodeForInstr(const MCInst &MI,
SmallVectorImpl<MCFixup> &Fixups) const; SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
// getBranchJumpOpValue - Return binary encoding of the jump // getBranchJumpOpValue - Return binary encoding of the jump
// target operand. If the machine operand requires relocation, // target operand. If the machine operand requires relocation,
// record the relocation and return zero. // record the relocation and return zero.
unsigned getJumpTargetOpValue(const MCInst &MI, unsigned OpNo, unsigned getJumpTargetOpValue(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups) const; SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
// getBranchJumpOpValueMM - Return binary encoding of the microMIPS jump // getBranchJumpOpValueMM - Return binary encoding of the microMIPS jump
// target operand. If the machine operand requires relocation, // target operand. If the machine operand requires relocation,
// record the relocation and return zero. // record the relocation and return zero.
unsigned getJumpTargetOpValueMM(const MCInst &MI, unsigned OpNo, unsigned getJumpTargetOpValueMM(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups) const; SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
// getBranchTargetOpValue - Return binary encoding of the branch // getBranchTargetOpValue - Return binary encoding of the branch
// target operand. If the machine operand requires relocation, // target operand. If the machine operand requires relocation,
// record the relocation and return zero. // record the relocation and return zero.
unsigned getBranchTargetOpValue(const MCInst &MI, unsigned OpNo, unsigned getBranchTargetOpValue(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups) const; SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
// getBranchTargetOpValue - Return binary encoding of the microMIPS branch // getBranchTargetOpValue - Return binary encoding of the microMIPS branch
// target operand. If the machine operand requires relocation, // target operand. If the machine operand requires relocation,
// record the relocation and return zero. // record the relocation and return zero.
unsigned getBranchTargetOpValueMM(const MCInst &MI, unsigned OpNo, unsigned getBranchTargetOpValueMM(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups) const; SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
// getMachineOpValue - Return binary encoding of operand. If the machin // getMachineOpValue - Return binary encoding of operand. If the machin
// operand requires relocation, record the relocation and return zero. // operand requires relocation, record the relocation and return zero.
unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO, unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO,
SmallVectorImpl<MCFixup> &Fixups) const; SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
unsigned getMSAMemEncoding(const MCInst &MI, unsigned OpNo, unsigned getMSAMemEncoding(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups) const; SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
unsigned getMemEncoding(const MCInst &MI, unsigned OpNo, unsigned getMemEncoding(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups) const; SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
unsigned getMemEncodingMMImm12(const MCInst &MI, unsigned OpNo, unsigned getMemEncodingMMImm12(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups) const; SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
unsigned getSizeExtEncoding(const MCInst &MI, unsigned OpNo, unsigned getSizeExtEncoding(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups) const; SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
unsigned getSizeInsEncoding(const MCInst &MI, unsigned OpNo, unsigned getSizeInsEncoding(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups) const; SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
// getLSAImmEncoding - Return binary encoding of LSA immediate. // getLSAImmEncoding - Return binary encoding of LSA immediate.
unsigned getLSAImmEncoding(const MCInst &MI, unsigned OpNo, unsigned getLSAImmEncoding(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups) const; SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
unsigned unsigned
getExprOpValue(const MCExpr *Expr,SmallVectorImpl<MCFixup> &Fixups) const; getExprOpValue(const MCExpr *Expr,SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
}; // class MipsMCCodeEmitter }; // class MipsMCCodeEmitter
} // namespace } // namespace
@ -240,7 +253,7 @@ EncodeInstruction(const MCInst &MI, raw_ostream &OS,
} }
unsigned long N = Fixups.size(); unsigned long N = Fixups.size();
uint32_t Binary = getBinaryCodeForInstr(TmpInst, Fixups); uint32_t Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI);
// Check for unimplemented opcodes. // Check for unimplemented opcodes.
// Unfortunately in MIPS both NOP and SLL will come in with Binary == 0 // Unfortunately in MIPS both NOP and SLL will come in with Binary == 0
@ -256,7 +269,7 @@ EncodeInstruction(const MCInst &MI, raw_ostream &OS,
Fixups.pop_back(); Fixups.pop_back();
Opcode = NewOpcode; Opcode = NewOpcode;
TmpInst.setOpcode (NewOpcode); TmpInst.setOpcode (NewOpcode);
Binary = getBinaryCodeForInstr(TmpInst, Fixups); Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI);
} }
} }
@ -275,7 +288,8 @@ EncodeInstruction(const MCInst &MI, raw_ostream &OS,
/// record the relocation and return zero. /// record the relocation and return zero.
unsigned MipsMCCodeEmitter:: unsigned MipsMCCodeEmitter::
getBranchTargetOpValue(const MCInst &MI, unsigned OpNo, getBranchTargetOpValue(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups) const { SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
const MCOperand &MO = MI.getOperand(OpNo); const MCOperand &MO = MI.getOperand(OpNo);
@ -296,7 +310,8 @@ getBranchTargetOpValue(const MCInst &MI, unsigned OpNo,
/// record the relocation and return zero. /// record the relocation and return zero.
unsigned MipsMCCodeEmitter:: unsigned MipsMCCodeEmitter::
getBranchTargetOpValueMM(const MCInst &MI, unsigned OpNo, getBranchTargetOpValueMM(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups) const { SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
const MCOperand &MO = MI.getOperand(OpNo); const MCOperand &MO = MI.getOperand(OpNo);
@ -318,7 +333,8 @@ getBranchTargetOpValueMM(const MCInst &MI, unsigned OpNo,
/// record the relocation and return zero. /// record the relocation and return zero.
unsigned MipsMCCodeEmitter:: unsigned MipsMCCodeEmitter::
getJumpTargetOpValue(const MCInst &MI, unsigned OpNo, getJumpTargetOpValue(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups) const { SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
const MCOperand &MO = MI.getOperand(OpNo); const MCOperand &MO = MI.getOperand(OpNo);
// If the destination is an immediate, divide by 4. // If the destination is an immediate, divide by 4.
@ -335,7 +351,8 @@ getJumpTargetOpValue(const MCInst &MI, unsigned OpNo,
unsigned MipsMCCodeEmitter:: unsigned MipsMCCodeEmitter::
getJumpTargetOpValueMM(const MCInst &MI, unsigned OpNo, getJumpTargetOpValueMM(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups) const { SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
const MCOperand &MO = MI.getOperand(OpNo); const MCOperand &MO = MI.getOperand(OpNo);
// If the destination is an immediate, divide by 2. // If the destination is an immediate, divide by 2.
@ -351,7 +368,8 @@ getJumpTargetOpValueMM(const MCInst &MI, unsigned OpNo,
} }
unsigned MipsMCCodeEmitter:: unsigned MipsMCCodeEmitter::
getExprOpValue(const MCExpr *Expr,SmallVectorImpl<MCFixup> &Fixups) const { getExprOpValue(const MCExpr *Expr,SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
int64_t Res; int64_t Res;
if (Expr->EvaluateAsAbsolute(Res)) if (Expr->EvaluateAsAbsolute(Res))
@ -363,8 +381,8 @@ getExprOpValue(const MCExpr *Expr,SmallVectorImpl<MCFixup> &Fixups) const {
} }
if (Kind == MCExpr::Binary) { if (Kind == MCExpr::Binary) {
unsigned Res = getExprOpValue(cast<MCBinaryExpr>(Expr)->getLHS(), Fixups); unsigned Res = getExprOpValue(cast<MCBinaryExpr>(Expr)->getLHS(), Fixups, STI);
Res += getExprOpValue(cast<MCBinaryExpr>(Expr)->getRHS(), Fixups); Res += getExprOpValue(cast<MCBinaryExpr>(Expr)->getRHS(), Fixups, STI);
return Res; return Res;
} }
if (Kind == MCExpr::SymbolRef) { if (Kind == MCExpr::SymbolRef) {
@ -471,7 +489,8 @@ getExprOpValue(const MCExpr *Expr,SmallVectorImpl<MCFixup> &Fixups) const {
/// operand requires relocation, record the relocation and return zero. /// operand requires relocation, record the relocation and return zero.
unsigned MipsMCCodeEmitter:: unsigned MipsMCCodeEmitter::
getMachineOpValue(const MCInst &MI, const MCOperand &MO, getMachineOpValue(const MCInst &MI, const MCOperand &MO,
SmallVectorImpl<MCFixup> &Fixups) const { SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
if (MO.isReg()) { if (MO.isReg()) {
unsigned Reg = MO.getReg(); unsigned Reg = MO.getReg();
unsigned RegNo = Ctx.getRegisterInfo()->getEncodingValue(Reg); unsigned RegNo = Ctx.getRegisterInfo()->getEncodingValue(Reg);
@ -484,18 +503,19 @@ getMachineOpValue(const MCInst &MI, const MCOperand &MO,
} }
// MO must be an Expr. // MO must be an Expr.
assert(MO.isExpr()); assert(MO.isExpr());
return getExprOpValue(MO.getExpr(),Fixups); return getExprOpValue(MO.getExpr(),Fixups, STI);
} }
/// getMSAMemEncoding - Return binary encoding of memory operand for LD/ST /// getMSAMemEncoding - Return binary encoding of memory operand for LD/ST
/// instructions. /// instructions.
unsigned unsigned
MipsMCCodeEmitter::getMSAMemEncoding(const MCInst &MI, unsigned OpNo, MipsMCCodeEmitter::getMSAMemEncoding(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups) const { SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
// Base register is encoded in bits 20-16, offset is encoded in bits 15-0. // Base register is encoded in bits 20-16, offset is encoded in bits 15-0.
assert(MI.getOperand(OpNo).isReg()); assert(MI.getOperand(OpNo).isReg());
unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo),Fixups) << 16; unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo),Fixups, STI) << 16;
unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups); unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI);
// The immediate field of an LD/ST instruction is scaled which means it must // The immediate field of an LD/ST instruction is scaled which means it must
// be divided (when encoding) by the size (in bytes) of the instructions' // be divided (when encoding) by the size (in bytes) of the instructions'
@ -534,31 +554,34 @@ MipsMCCodeEmitter::getMSAMemEncoding(const MCInst &MI, unsigned OpNo,
/// If the offset operand requires relocation, record the relocation. /// If the offset operand requires relocation, record the relocation.
unsigned unsigned
MipsMCCodeEmitter::getMemEncoding(const MCInst &MI, unsigned OpNo, MipsMCCodeEmitter::getMemEncoding(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups) const { SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
// Base register is encoded in bits 20-16, offset is encoded in bits 15-0. // Base register is encoded in bits 20-16, offset is encoded in bits 15-0.
assert(MI.getOperand(OpNo).isReg()); assert(MI.getOperand(OpNo).isReg());
unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo),Fixups) << 16; unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo),Fixups, STI) << 16;
unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups); unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI);
return (OffBits & 0xFFFF) | RegBits; return (OffBits & 0xFFFF) | RegBits;
} }
unsigned MipsMCCodeEmitter:: unsigned MipsMCCodeEmitter::
getMemEncodingMMImm12(const MCInst &MI, unsigned OpNo, getMemEncodingMMImm12(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups) const { SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
// Base register is encoded in bits 20-16, offset is encoded in bits 11-0. // Base register is encoded in bits 20-16, offset is encoded in bits 11-0.
assert(MI.getOperand(OpNo).isReg()); assert(MI.getOperand(OpNo).isReg());
unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups) << 16; unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI) << 16;
unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups); unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI);
return (OffBits & 0x0FFF) | RegBits; return (OffBits & 0x0FFF) | RegBits;
} }
unsigned unsigned
MipsMCCodeEmitter::getSizeExtEncoding(const MCInst &MI, unsigned OpNo, MipsMCCodeEmitter::getSizeExtEncoding(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups) const { SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
assert(MI.getOperand(OpNo).isImm()); assert(MI.getOperand(OpNo).isImm());
unsigned SizeEncoding = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups); unsigned SizeEncoding = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI);
return SizeEncoding - 1; return SizeEncoding - 1;
} }
@ -566,21 +589,23 @@ MipsMCCodeEmitter::getSizeExtEncoding(const MCInst &MI, unsigned OpNo,
// //
unsigned unsigned
MipsMCCodeEmitter::getSizeInsEncoding(const MCInst &MI, unsigned OpNo, MipsMCCodeEmitter::getSizeInsEncoding(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups) const { SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
assert(MI.getOperand(OpNo-1).isImm()); assert(MI.getOperand(OpNo-1).isImm());
assert(MI.getOperand(OpNo).isImm()); assert(MI.getOperand(OpNo).isImm());
unsigned Position = getMachineOpValue(MI, MI.getOperand(OpNo-1), Fixups); unsigned Position = getMachineOpValue(MI, MI.getOperand(OpNo-1), Fixups, STI);
unsigned Size = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups); unsigned Size = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI);
return Position + Size - 1; return Position + Size - 1;
} }
unsigned unsigned
MipsMCCodeEmitter::getLSAImmEncoding(const MCInst &MI, unsigned OpNo, MipsMCCodeEmitter::getLSAImmEncoding(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups) const { SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
assert(MI.getOperand(OpNo).isImm()); assert(MI.getOperand(OpNo).isImm());
// The immediate is encoded as 'immediate - 1'. // The immediate is encoded as 'immediate - 1'.
return getMachineOpValue(MI, MI.getOperand(OpNo), Fixups) - 1; return getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI) - 1;
} }
#include "MipsGenMCCodeEmitter.inc" #include "MipsGenMCCodeEmitter.inc"

93
lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp
View File

@ -46,35 +46,47 @@ public:
~PPCMCCodeEmitter() {} ~PPCMCCodeEmitter() {}
unsigned getDirectBrEncoding(const MCInst &MI, unsigned OpNo, unsigned getDirectBrEncoding(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups) const; SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
unsigned getCondBrEncoding(const MCInst &MI, unsigned OpNo, unsigned getCondBrEncoding(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups) const; SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
unsigned getAbsDirectBrEncoding(const MCInst &MI, unsigned OpNo, unsigned getAbsDirectBrEncoding(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups) const; SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
unsigned getAbsCondBrEncoding(const MCInst &MI, unsigned OpNo, unsigned getAbsCondBrEncoding(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups) const; SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
unsigned getImm16Encoding(const MCInst &MI, unsigned OpNo, unsigned getImm16Encoding(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups) const; SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
unsigned getMemRIEncoding(const MCInst &MI, unsigned OpNo, unsigned getMemRIEncoding(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups) const; SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
unsigned getMemRIXEncoding(const MCInst &MI, unsigned OpNo, unsigned getMemRIXEncoding(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups) const; SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
unsigned getTLSRegEncoding(const MCInst &MI, unsigned OpNo, unsigned getTLSRegEncoding(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups) const; SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
unsigned getTLSCallEncoding(const MCInst &MI, unsigned OpNo, unsigned getTLSCallEncoding(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups) const; SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
unsigned get_crbitm_encoding(const MCInst &MI, unsigned OpNo, unsigned get_crbitm_encoding(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups) const; SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
/// getMachineOpValue - Return binary encoding of operand. If the machine /// getMachineOpValue - Return binary encoding of operand. If the machine
/// operand requires relocation, record the relocation and return zero. /// operand requires relocation, record the relocation and return zero.
unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO, unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO,
SmallVectorImpl<MCFixup> &Fixups) const; SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
// getBinaryCodeForInstr - TableGen'erated function for getting the // getBinaryCodeForInstr - TableGen'erated function for getting the
// binary encoding for an instruction. // binary encoding for an instruction.
uint64_t getBinaryCodeForInstr(const MCInst &MI, uint64_t getBinaryCodeForInstr(const MCInst &MI,
SmallVectorImpl<MCFixup> &Fixups) const; SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
void EncodeInstruction(const MCInst &MI, raw_ostream &OS, void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
SmallVectorImpl<MCFixup> &Fixups, SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const { const MCSubtargetInfo &STI) const {
@ -85,7 +97,7 @@ public:
if (Opcode == TargetOpcode::COPY_TO_REGCLASS) if (Opcode == TargetOpcode::COPY_TO_REGCLASS)
return; return;
uint64_t Bits = getBinaryCodeForInstr(MI, Fixups); uint64_t Bits = getBinaryCodeForInstr(MI, Fixups, STI);
// BL8_NOP etc. all have a size of 8 because of the following 'nop'. // BL8_NOP etc. all have a size of 8 because of the following 'nop'.
unsigned Size = 4; // FIXME: Have Desc.getSize() return the correct value! unsigned Size = 4; // FIXME: Have Desc.getSize() return the correct value!
@ -116,9 +128,10 @@ MCCodeEmitter *llvm::createPPCMCCodeEmitter(const MCInstrInfo &MCII,
unsigned PPCMCCodeEmitter:: unsigned PPCMCCodeEmitter::
getDirectBrEncoding(const MCInst &MI, unsigned OpNo, getDirectBrEncoding(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups) const { SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
const MCOperand &MO = MI.getOperand(OpNo); const MCOperand &MO = MI.getOperand(OpNo);
if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups); if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI);
// Add a fixup for the branch target. // Add a fixup for the branch target.
Fixups.push_back(MCFixup::Create(0, MO.getExpr(), Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
@ -127,9 +140,10 @@ getDirectBrEncoding(const MCInst &MI, unsigned OpNo,
} }
unsigned PPCMCCodeEmitter::getCondBrEncoding(const MCInst &MI, unsigned OpNo, unsigned PPCMCCodeEmitter::getCondBrEncoding(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups) const { SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
const MCOperand &MO = MI.getOperand(OpNo); const MCOperand &MO = MI.getOperand(OpNo);
if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups); if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI);
// Add a fixup for the branch target. // Add a fixup for the branch target.
Fixups.push_back(MCFixup::Create(0, MO.getExpr(), Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
@ -139,9 +153,10 @@ unsigned PPCMCCodeEmitter::getCondBrEncoding(const MCInst &MI, unsigned OpNo,
unsigned PPCMCCodeEmitter:: unsigned PPCMCCodeEmitter::
getAbsDirectBrEncoding(const MCInst &MI, unsigned OpNo, getAbsDirectBrEncoding(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups) const { SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
const MCOperand &MO = MI.getOperand(OpNo); const MCOperand &MO = MI.getOperand(OpNo);
if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups); if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI);
// Add a fixup for the branch target. // Add a fixup for the branch target.
Fixups.push_back(MCFixup::Create(0, MO.getExpr(), Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
@ -151,9 +166,10 @@ getAbsDirectBrEncoding(const MCInst &MI, unsigned OpNo,
unsigned PPCMCCodeEmitter:: unsigned PPCMCCodeEmitter::
getAbsCondBrEncoding(const MCInst &MI, unsigned OpNo, getAbsCondBrEncoding(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups) const { SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
const MCOperand &MO = MI.getOperand(OpNo); const MCOperand &MO = MI.getOperand(OpNo);
if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups); if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI);
// Add a fixup for the branch target. // Add a fixup for the branch target.
Fixups.push_back(MCFixup::Create(0, MO.getExpr(), Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
@ -162,9 +178,10 @@ getAbsCondBrEncoding(const MCInst &MI, unsigned OpNo,
} }
unsigned PPCMCCodeEmitter::getImm16Encoding(const MCInst &MI, unsigned OpNo, unsigned PPCMCCodeEmitter::getImm16Encoding(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups) const { SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
const MCOperand &MO = MI.getOperand(OpNo); const MCOperand &MO = MI.getOperand(OpNo);
if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups); if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI);
// Add a fixup for the immediate field. // Add a fixup for the immediate field.
Fixups.push_back(MCFixup::Create(2, MO.getExpr(), Fixups.push_back(MCFixup::Create(2, MO.getExpr(),
@ -173,15 +190,16 @@ unsigned PPCMCCodeEmitter::getImm16Encoding(const MCInst &MI, unsigned OpNo,
} }
unsigned PPCMCCodeEmitter::getMemRIEncoding(const MCInst &MI, unsigned OpNo, unsigned PPCMCCodeEmitter::getMemRIEncoding(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups) const { SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
// Encode (imm, reg) as a memri, which has the low 16-bits as the // Encode (imm, reg) as a memri, which has the low 16-bits as the
// displacement and the next 5 bits as the register #. // displacement and the next 5 bits as the register #.
assert(MI.getOperand(OpNo+1).isReg()); assert(MI.getOperand(OpNo+1).isReg());
unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups) << 16; unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 16;
const MCOperand &MO = MI.getOperand(OpNo); const MCOperand &MO = MI.getOperand(OpNo);
if (MO.isImm()) if (MO.isImm())
return (getMachineOpValue(MI, MO, Fixups) & 0xFFFF) | RegBits; return (getMachineOpValue(MI, MO, Fixups, STI) & 0xFFFF) | RegBits;
// Add a fixup for the displacement field. // Add a fixup for the displacement field.
Fixups.push_back(MCFixup::Create(2, MO.getExpr(), Fixups.push_back(MCFixup::Create(2, MO.getExpr(),
@ -191,15 +209,16 @@ unsigned PPCMCCodeEmitter::getMemRIEncoding(const MCInst &MI, unsigned OpNo,
unsigned PPCMCCodeEmitter::getMemRIXEncoding(const MCInst &MI, unsigned OpNo, unsigned PPCMCCodeEmitter::getMemRIXEncoding(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups) const { SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
// Encode (imm, reg) as a memrix, which has the low 14-bits as the // Encode (imm, reg) as a memrix, which has the low 14-bits as the
// displacement and the next 5 bits as the register #. // displacement and the next 5 bits as the register #.
assert(MI.getOperand(OpNo+1).isReg()); assert(MI.getOperand(OpNo+1).isReg());
unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups) << 14; unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 14;
const MCOperand &MO = MI.getOperand(OpNo); const MCOperand &MO = MI.getOperand(OpNo);
if (MO.isImm()) if (MO.isImm())
return ((getMachineOpValue(MI, MO, Fixups) >> 2) & 0x3FFF) | RegBits; return ((getMachineOpValue(MI, MO, Fixups, STI) >> 2) & 0x3FFF) | RegBits;
// Add a fixup for the displacement field. // Add a fixup for the displacement field.
Fixups.push_back(MCFixup::Create(2, MO.getExpr(), Fixups.push_back(MCFixup::Create(2, MO.getExpr(),
@ -209,9 +228,10 @@ unsigned PPCMCCodeEmitter::getMemRIXEncoding(const MCInst &MI, unsigned OpNo,
unsigned PPCMCCodeEmitter::getTLSRegEncoding(const MCInst &MI, unsigned OpNo, unsigned PPCMCCodeEmitter::getTLSRegEncoding(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups) const { SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
const MCOperand &MO = MI.getOperand(OpNo); const MCOperand &MO = MI.getOperand(OpNo);
if (MO.isReg()) return getMachineOpValue(MI, MO, Fixups); if (MO.isReg()) return getMachineOpValue(MI, MO, Fixups, STI);
// Add a fixup for the TLS register, which simply provides a relocation // Add a fixup for the TLS register, which simply provides a relocation
// hint to the linker that this statement is part of a relocation sequence. // hint to the linker that this statement is part of a relocation sequence.
@ -223,19 +243,21 @@ unsigned PPCMCCodeEmitter::getTLSRegEncoding(const MCInst &MI, unsigned OpNo,
} }
unsigned PPCMCCodeEmitter::getTLSCallEncoding(const MCInst &MI, unsigned OpNo, unsigned PPCMCCodeEmitter::getTLSCallEncoding(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups) const { SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
// For special TLS calls, we need two fixups; one for the branch target // For special TLS calls, we need two fixups; one for the branch target
// (__tls_get_addr), which we create via getDirectBrEncoding as usual, // (__tls_get_addr), which we create via getDirectBrEncoding as usual,
// and one for the TLSGD or TLSLD symbol, which is emitted here. // and one for the TLSGD or TLSLD symbol, which is emitted here.
const MCOperand &MO = MI.getOperand(OpNo+1); const MCOperand &MO = MI.getOperand(OpNo+1);
Fixups.push_back(MCFixup::Create(0, MO.getExpr(), Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
(MCFixupKind)PPC::fixup_ppc_nofixup)); (MCFixupKind)PPC::fixup_ppc_nofixup));
return getDirectBrEncoding(MI, OpNo, Fixups); return getDirectBrEncoding(MI, OpNo, Fixups, STI);
} }
unsigned PPCMCCodeEmitter:: unsigned PPCMCCodeEmitter::
get_crbitm_encoding(const MCInst &MI, unsigned OpNo, get_crbitm_encoding(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups) const { SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
const MCOperand &MO = MI.getOperand(OpNo); const MCOperand &MO = MI.getOperand(OpNo);
assert((MI.getOpcode() == PPC::MTOCRF || MI.getOpcode() == PPC::MTOCRF8 || assert((MI.getOpcode() == PPC::MTOCRF || MI.getOpcode() == PPC::MTOCRF8 ||
MI.getOpcode() == PPC::MFOCRF || MI.getOpcode() == PPC::MFOCRF8) && MI.getOpcode() == PPC::MFOCRF || MI.getOpcode() == PPC::MFOCRF8) &&
@ -246,7 +268,8 @@ get_crbitm_encoding(const MCInst &MI, unsigned OpNo,
unsigned PPCMCCodeEmitter:: unsigned PPCMCCodeEmitter::
getMachineOpValue(const MCInst &MI, const MCOperand &MO, getMachineOpValue(const MCInst &MI, const MCOperand &MO,
SmallVectorImpl<MCFixup> &Fixups) const { SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
if (MO.isReg()) { if (MO.isReg()) {
// MTOCRF/MFOCRF should go through get_crbitm_encoding for the CR operand. // MTOCRF/MFOCRF should go through get_crbitm_encoding for the CR operand.
// The GPR operand should come through here though. // The GPR operand should come through here though.

7
lib/Target/R600/MCTargetDesc/AMDGPUMCCodeEmitter.h
View File

@ -22,16 +22,19 @@ namespace llvm {
class MCInst; class MCInst;
class MCOperand; class MCOperand;
class MCSubtargetInfo;
class AMDGPUMCCodeEmitter : public MCCodeEmitter { class AMDGPUMCCodeEmitter : public MCCodeEmitter {
virtual void anchor(); virtual void anchor();
public: public:
uint64_t getBinaryCodeForInstr(const MCInst &MI, uint64_t getBinaryCodeForInstr(const MCInst &MI,
SmallVectorImpl<MCFixup> &Fixups) const; SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
virtual uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO, virtual uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO,
SmallVectorImpl<MCFixup> &Fixups) const { SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
return 0; return 0;
} }
}; };

12
lib/Target/R600/MCTargetDesc/R600MCCodeEmitter.cpp
View File

@ -49,7 +49,8 @@ public:
/// \returns the encoding for an MCOperand. /// \returns the encoding for an MCOperand.
virtual uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO, virtual uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO,
SmallVectorImpl<MCFixup> &Fixups) const; SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
private: private:
void EmitByte(unsigned int byte, raw_ostream &OS) const; void EmitByte(unsigned int byte, raw_ostream &OS) const;
@ -98,7 +99,7 @@ void R600MCCodeEmitter::EncodeInstruction(const MCInst &MI, raw_ostream &OS,
MI.getOpcode() == AMDGPU::KILL) { MI.getOpcode() == AMDGPU::KILL) {
return; return;
} else if (IS_VTX(Desc)) { } else if (IS_VTX(Desc)) {
uint64_t InstWord01 = getBinaryCodeForInstr(MI, Fixups); uint64_t InstWord01 = getBinaryCodeForInstr(MI, Fixups, STI);
uint32_t InstWord2 = MI.getOperand(2).getImm(); // Offset uint32_t InstWord2 = MI.getOperand(2).getImm(); // Offset
if (!(STI.getFeatureBits() & AMDGPU::FeatureCaymanISA)) { if (!(STI.getFeatureBits() & AMDGPU::FeatureCaymanISA)) {
InstWord2 |= 1 << 19; // Mega-Fetch bit InstWord2 |= 1 << 19; // Mega-Fetch bit
@ -122,7 +123,7 @@ void R600MCCodeEmitter::EncodeInstruction(const MCInst &MI, raw_ostream &OS,
MI.getOperand(8).getImm() & 0x1F MI.getOperand(8).getImm() & 0x1F
}; };
uint64_t Word01 = getBinaryCodeForInstr(MI, Fixups); uint64_t Word01 = getBinaryCodeForInstr(MI, Fixups, STI);
uint32_t Word2 = Sampler << 15 | SrcSelect[ELEMENT_X] << 20 | uint32_t Word2 = Sampler << 15 | SrcSelect[ELEMENT_X] << 20 |
SrcSelect[ELEMENT_Y] << 23 | SrcSelect[ELEMENT_Z] << 26 | SrcSelect[ELEMENT_Y] << 23 | SrcSelect[ELEMENT_Z] << 26 |
SrcSelect[ELEMENT_W] << 29 | Offsets[0] << 0 | Offsets[1] << 5 | SrcSelect[ELEMENT_W] << 29 | Offsets[0] << 0 | Offsets[1] << 5 |
@ -132,7 +133,7 @@ void R600MCCodeEmitter::EncodeInstruction(const MCInst &MI, raw_ostream &OS,
Emit(Word2, OS); Emit(Word2, OS);
Emit((uint32_t) 0, OS); Emit((uint32_t) 0, OS);
} else { } else {
uint64_t Inst = getBinaryCodeForInstr(MI, Fixups); uint64_t Inst = getBinaryCodeForInstr(MI, Fixups, STI);
if ((STI.getFeatureBits() & AMDGPU::FeatureR600ALUInst) && if ((STI.getFeatureBits() & AMDGPU::FeatureR600ALUInst) &&
((Desc.TSFlags & R600_InstFlag::OP1) || ((Desc.TSFlags & R600_InstFlag::OP1) ||
Desc.TSFlags & R600_InstFlag::OP2)) { Desc.TSFlags & R600_InstFlag::OP2)) {
@ -170,7 +171,8 @@ unsigned R600MCCodeEmitter::getHWReg(unsigned RegNo) const {
uint64_t R600MCCodeEmitter::getMachineOpValue(const MCInst &MI, uint64_t R600MCCodeEmitter::getMachineOpValue(const MCInst &MI,
const MCOperand &MO, const MCOperand &MO,
SmallVectorImpl<MCFixup> &Fixup) const { SmallVectorImpl<MCFixup> &Fixup,
const MCSubtargetInfo &STI) const {
if (MO.isReg()) { if (MO.isReg()) {
if (HAS_NATIVE_OPERANDS(MCII.get(MI.getOpcode()).TSFlags)) { if (HAS_NATIVE_OPERANDS(MCII.get(MI.getOpcode()).TSFlags)) {
return MRI.getEncodingValue(MO.getReg()); return MRI.getEncodingValue(MO.getReg());

8
lib/Target/R600/MCTargetDesc/SIMCCodeEmitter.cpp
View File

@ -60,7 +60,8 @@ public:
/// \returns the encoding for an MCOperand. /// \returns the encoding for an MCOperand.
virtual uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO, virtual uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO,
SmallVectorImpl<MCFixup> &Fixups) const; SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
}; };
} // End anonymous namespace } // End anonymous namespace
@ -129,7 +130,7 @@ void SIMCCodeEmitter::EncodeInstruction(const MCInst &MI, raw_ostream &OS,
SmallVectorImpl<MCFixup> &Fixups, SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const { const MCSubtargetInfo &STI) const {
uint64_t Encoding = getBinaryCodeForInstr(MI, Fixups); uint64_t Encoding = getBinaryCodeForInstr(MI, Fixups, STI);
const MCInstrDesc &Desc = MCII.get(MI.getOpcode()); const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
unsigned bytes = Desc.getSize(); unsigned bytes = Desc.getSize();
@ -170,7 +171,8 @@ void SIMCCodeEmitter::EncodeInstruction(const MCInst &MI, raw_ostream &OS,
uint64_t SIMCCodeEmitter::getMachineOpValue(const MCInst &MI, uint64_t SIMCCodeEmitter::getMachineOpValue(const MCInst &MI,
const MCOperand &MO, const MCOperand &MO,
SmallVectorImpl<MCFixup> &Fixups) const { SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
if (MO.isReg()) if (MO.isReg())
return MRI.getEncodingValue(MO.getReg()); return MRI.getEncodingValue(MO.getReg());

27
lib/Target/Sparc/MCTargetDesc/SparcMCCodeEmitter.cpp
View File

@ -45,17 +45,21 @@ public:
// getBinaryCodeForInstr - TableGen'erated function for getting the // getBinaryCodeForInstr - TableGen'erated function for getting the
// binary encoding for an instruction. // binary encoding for an instruction.
uint64_t getBinaryCodeForInstr(const MCInst &MI, uint64_t getBinaryCodeForInstr(const MCInst &MI,
SmallVectorImpl<MCFixup> &Fixups) const; SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
/// getMachineOpValue - Return binary encoding of operand. If the machine /// getMachineOpValue - Return binary encoding of operand. If the machine
/// operand requires relocation, record the relocation and return zero. /// operand requires relocation, record the relocation and return zero.
unsigned getMachineOpValue(const MCInst &MI, const MCOperand &MO, unsigned getMachineOpValue(const MCInst &MI, const MCOperand &MO,
SmallVectorImpl<MCFixup> &Fixups) const; SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
unsigned getCallTargetOpValue(const MCInst &MI, unsigned OpNo, unsigned getCallTargetOpValue(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups) const; SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
unsigned getBranchTargetOpValue(const MCInst &MI, unsigned OpNo, unsigned getBranchTargetOpValue(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups) const; SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
}; };
} // end anonymous namespace } // end anonymous namespace
@ -71,7 +75,7 @@ void SparcMCCodeEmitter::
EncodeInstruction(const MCInst &MI, raw_ostream &OS, EncodeInstruction(const MCInst &MI, raw_ostream &OS,
SmallVectorImpl<MCFixup> &Fixups, SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const { const MCSubtargetInfo &STI) const {
unsigned Bits = getBinaryCodeForInstr(MI, Fixups); unsigned Bits = getBinaryCodeForInstr(MI, Fixups, STI);
// Output the constant in big endian byte order. // Output the constant in big endian byte order.
for (unsigned i = 0; i != 4; ++i) { for (unsigned i = 0; i != 4; ++i) {
@ -85,7 +89,8 @@ EncodeInstruction(const MCInst &MI, raw_ostream &OS,
unsigned SparcMCCodeEmitter:: unsigned SparcMCCodeEmitter::
getMachineOpValue(const MCInst &MI, const MCOperand &MO, getMachineOpValue(const MCInst &MI, const MCOperand &MO,
SmallVectorImpl<MCFixup> &Fixups) const { SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
if (MO.isReg()) if (MO.isReg())
return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg()); return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg());
@ -140,10 +145,11 @@ getMachineOpValue(const MCInst &MI, const MCOperand &MO,
unsigned SparcMCCodeEmitter:: unsigned SparcMCCodeEmitter::
getCallTargetOpValue(const MCInst &MI, unsigned OpNo, getCallTargetOpValue(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups) const { SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
const MCOperand &MO = MI.getOperand(OpNo); const MCOperand &MO = MI.getOperand(OpNo);
if (MO.isReg() || MO.isImm()) if (MO.isReg() || MO.isImm())
return getMachineOpValue(MI, MO, Fixups); return getMachineOpValue(MI, MO, Fixups, STI);
Fixups.push_back(MCFixup::Create(0, MO.getExpr(), Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
(MCFixupKind)Sparc::fixup_sparc_call30)); (MCFixupKind)Sparc::fixup_sparc_call30));
@ -152,10 +158,11 @@ getCallTargetOpValue(const MCInst &MI, unsigned OpNo,
unsigned SparcMCCodeEmitter:: unsigned SparcMCCodeEmitter::
getBranchTargetOpValue(const MCInst &MI, unsigned OpNo, getBranchTargetOpValue(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups) const { SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
const MCOperand &MO = MI.getOperand(OpNo); const MCOperand &MO = MI.getOperand(OpNo);
if (MO.isReg() || MO.isImm()) if (MO.isReg() || MO.isImm())
return getMachineOpValue(MI, MO, Fixups); return getMachineOpValue(MI, MO, Fixups, STI);
Sparc::Fixups fixup = Sparc::fixup_sparc_br22; Sparc::Fixups fixup = Sparc::fixup_sparc_br22;
if (MI.getOpcode() == SP::BPXCC) if (MI.getOpcode() == SP::BPXCC)

73
lib/Target/SystemZ/MCTargetDesc/SystemZMCCodeEmitter.cpp
View File

@ -42,27 +42,34 @@ public:
private: private:
// Automatically generated by TableGen. // Automatically generated by TableGen.
uint64_t getBinaryCodeForInstr(const MCInst &MI, uint64_t getBinaryCodeForInstr(const MCInst &MI,
SmallVectorImpl<MCFixup> &Fixups) const; SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
// Called by the TableGen code to get the binary encoding of operand // Called by the TableGen code to get the binary encoding of operand
// MO in MI. Fixups is the list of fixups against MI. // MO in MI. Fixups is the list of fixups against MI.
uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO, uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO,
SmallVectorImpl<MCFixup> &Fixups) const; SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
// Called by the TableGen code to get the binary encoding of an address. // Called by the TableGen code to get the binary encoding of an address.
// The index or length, if any, is encoded first, followed by the base, // The index or length, if any, is encoded first, followed by the base,
// followed by the displacement. In a 20-bit displacement, // followed by the displacement. In a 20-bit displacement,
// the low 12 bits are encoded before the high 8 bits. // the low 12 bits are encoded before the high 8 bits.
uint64_t getBDAddr12Encoding(const MCInst &MI, unsigned OpNum, uint64_t getBDAddr12Encoding(const MCInst &MI, unsigned OpNum,
SmallVectorImpl<MCFixup> &Fixups) const; SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
uint64_t getBDAddr20Encoding(const MCInst &MI, unsigned OpNum, uint64_t getBDAddr20Encoding(const MCInst &MI, unsigned OpNum,
SmallVectorImpl<MCFixup> &Fixups) const; SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
uint64_t getBDXAddr12Encoding(const MCInst &MI, unsigned OpNum, uint64_t getBDXAddr12Encoding(const MCInst &MI, unsigned OpNum,
SmallVectorImpl<MCFixup> &Fixups) const; SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
uint64_t getBDXAddr20Encoding(const MCInst &MI, unsigned OpNum, uint64_t getBDXAddr20Encoding(const MCInst &MI, unsigned OpNum,
SmallVectorImpl<MCFixup> &Fixups) const; SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
uint64_t getBDLAddr12Len8Encoding(const MCInst &MI, unsigned OpNum, uint64_t getBDLAddr12Len8Encoding(const MCInst &MI, unsigned OpNum,
SmallVectorImpl<MCFixup> &Fixups) const; SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
// Operand OpNum of MI needs a PC-relative fixup of kind Kind at // Operand OpNum of MI needs a PC-relative fixup of kind Kind at
// Offset bytes from the start of MI. Add the fixup to Fixups // Offset bytes from the start of MI. Add the fixup to Fixups
@ -73,11 +80,13 @@ private:
unsigned Kind, int64_t Offset) const; unsigned Kind, int64_t Offset) const;
uint64_t getPC16DBLEncoding(const MCInst &MI, unsigned OpNum, uint64_t getPC16DBLEncoding(const MCInst &MI, unsigned OpNum,
SmallVectorImpl<MCFixup> &Fixups) const { SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
return getPCRelEncoding(MI, OpNum, Fixups, SystemZ::FK_390_PC16DBL, 2); return getPCRelEncoding(MI, OpNum, Fixups, SystemZ::FK_390_PC16DBL, 2);
} }
uint64_t getPC32DBLEncoding(const MCInst &MI, unsigned OpNum, uint64_t getPC32DBLEncoding(const MCInst &MI, unsigned OpNum,
SmallVectorImpl<MCFixup> &Fixups) const { SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
return getPCRelEncoding(MI, OpNum, Fixups, SystemZ::FK_390_PC32DBL, 2); return getPCRelEncoding(MI, OpNum, Fixups, SystemZ::FK_390_PC32DBL, 2);
} }
}; };
@ -94,7 +103,7 @@ void SystemZMCCodeEmitter::
EncodeInstruction(const MCInst &MI, raw_ostream &OS, EncodeInstruction(const MCInst &MI, raw_ostream &OS,
SmallVectorImpl<MCFixup> &Fixups, SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const { const MCSubtargetInfo &STI) const {
uint64_t Bits = getBinaryCodeForInstr(MI, Fixups); uint64_t Bits = getBinaryCodeForInstr(MI, Fixups, STI);
unsigned Size = MCII.get(MI.getOpcode()).getSize(); unsigned Size = MCII.get(MI.getOpcode()).getSize();
// Big-endian insertion of Size bytes. // Big-endian insertion of Size bytes.
unsigned ShiftValue = (Size * 8) - 8; unsigned ShiftValue = (Size * 8) - 8;
@ -106,7 +115,8 @@ EncodeInstruction(const MCInst &MI, raw_ostream &OS,
uint64_t SystemZMCCodeEmitter:: uint64_t SystemZMCCodeEmitter::
getMachineOpValue(const MCInst &MI, const MCOperand &MO, getMachineOpValue(const MCInst &MI, const MCOperand &MO,
SmallVectorImpl<MCFixup> &Fixups) const { SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
if (MO.isReg()) if (MO.isReg())
return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg()); return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg());
if (MO.isImm()) if (MO.isImm())
@ -116,38 +126,42 @@ getMachineOpValue(const MCInst &MI, const MCOperand &MO,
uint64_t SystemZMCCodeEmitter:: uint64_t SystemZMCCodeEmitter::
getBDAddr12Encoding(const MCInst &MI, unsigned OpNum, getBDAddr12Encoding(const MCInst &MI, unsigned OpNum,
SmallVectorImpl<MCFixup> &Fixups) const { SmallVectorImpl<MCFixup> &Fixups,
uint64_t Base = getMachineOpValue(MI, MI.getOperand(OpNum), Fixups); const MCSubtargetInfo &STI) const {
uint64_t Disp = getMachineOpValue(MI, MI.getOperand(OpNum + 1), Fixups); uint64_t Base = getMachineOpValue(MI, MI.getOperand(OpNum), Fixups, STI);
uint64_t Disp = getMachineOpValue(MI, MI.getOperand(OpNum + 1), Fixups, STI);
assert(isUInt<4>(Base) && isUInt<12>(Disp)); assert(isUInt<4>(Base) && isUInt<12>(Disp));
return (Base << 12) | Disp; return (Base << 12) | Disp;
} }
uint64_t SystemZMCCodeEmitter:: uint64_t SystemZMCCodeEmitter::
getBDAddr20Encoding(const MCInst &MI, unsigned OpNum, getBDAddr20Encoding(const MCInst &MI, unsigned OpNum,
SmallVectorImpl<MCFixup> &Fixups) const { SmallVectorImpl<MCFixup> &Fixups,
uint64_t Base = getMachineOpValue(MI, MI.getOperand(OpNum), Fixups); const MCSubtargetInfo &STI) const {
uint64_t Disp = getMachineOpValue(MI, MI.getOperand(OpNum + 1), Fixups); uint64_t Base = getMachineOpValue(MI, MI.getOperand(OpNum), Fixups, STI);
uint64_t Disp = getMachineOpValue(MI, MI.getOperand(OpNum + 1), Fixups, STI);
assert(isUInt<4>(Base) && isInt<20>(Disp)); assert(isUInt<4>(Base) && isInt<20>(Disp));
return (Base << 20) | ((Disp & 0xfff) << 8) | ((Disp & 0xff000) >> 12); return (Base << 20) | ((Disp & 0xfff) << 8) | ((Disp & 0xff000) >> 12);
} }
uint64_t SystemZMCCodeEmitter:: uint64_t SystemZMCCodeEmitter::
getBDXAddr12Encoding(const MCInst &MI, unsigned OpNum, getBDXAddr12Encoding(const MCInst &MI, unsigned OpNum,
SmallVectorImpl<MCFixup> &Fixups) const { SmallVectorImpl<MCFixup> &Fixups,
uint64_t Base = getMachineOpValue(MI, MI.getOperand(OpNum), Fixups); const MCSubtargetInfo &STI) const {
uint64_t Disp = getMachineOpValue(MI, MI.getOperand(OpNum + 1), Fixups); uint64_t Base = getMachineOpValue(MI, MI.getOperand(OpNum), Fixups, STI);
uint64_t Index = getMachineOpValue(MI, MI.getOperand(OpNum + 2), Fixups); uint64_t Disp = getMachineOpValue(MI, MI.getOperand(OpNum + 1), Fixups, STI);
uint64_t Index = getMachineOpValue(MI, MI.getOperand(OpNum + 2), Fixups, STI);
assert(isUInt<4>(Base) && isUInt<12>(Disp) && isUInt<4>(Index)); assert(isUInt<4>(Base) && isUInt<12>(Disp) && isUInt<4>(Index));
return (Index << 16) | (Base << 12) | Disp; return (Index << 16) | (Base << 12) | Disp;
} }
uint64_t SystemZMCCodeEmitter:: uint64_t SystemZMCCodeEmitter::
getBDXAddr20Encoding(const MCInst &MI, unsigned OpNum, getBDXAddr20Encoding(const MCInst &MI, unsigned OpNum,
SmallVectorImpl<MCFixup> &Fixups) const { SmallVectorImpl<MCFixup> &Fixups,
uint64_t Base = getMachineOpValue(MI, MI.getOperand(OpNum), Fixups); const MCSubtargetInfo &STI) const {
uint64_t Disp = getMachineOpValue(MI, MI.getOperand(OpNum + 1), Fixups); uint64_t Base = getMachineOpValue(MI, MI.getOperand(OpNum), Fixups, STI);
uint64_t Index = getMachineOpValue(MI, MI.getOperand(OpNum + 2), Fixups); uint64_t Disp = getMachineOpValue(MI, MI.getOperand(OpNum + 1), Fixups, STI);
uint64_t Index = getMachineOpValue(MI, MI.getOperand(OpNum + 2), Fixups, STI);
assert(isUInt<4>(Base) && isInt<20>(Disp) && isUInt<4>(Index)); assert(isUInt<4>(Base) && isInt<20>(Disp) && isUInt<4>(Index));
return (Index << 24) | (Base << 20) | ((Disp & 0xfff) << 8) return (Index << 24) | (Base << 20) | ((Disp & 0xfff) << 8)
| ((Disp & 0xff000) >> 12); | ((Disp & 0xff000) >> 12);
@ -155,10 +169,11 @@ getBDXAddr20Encoding(const MCInst &MI, unsigned OpNum,
uint64_t SystemZMCCodeEmitter:: uint64_t SystemZMCCodeEmitter::
getBDLAddr12Len8Encoding(const MCInst &MI, unsigned OpNum, getBDLAddr12Len8Encoding(const MCInst &MI, unsigned OpNum,
SmallVectorImpl<MCFixup> &Fixups) const { SmallVectorImpl<MCFixup> &Fixups,
uint64_t Base = getMachineOpValue(MI, MI.getOperand(OpNum), Fixups); const MCSubtargetInfo &STI) const {
uint64_t Disp = getMachineOpValue(MI, MI.getOperand(OpNum + 1), Fixups); uint64_t Base = getMachineOpValue(MI, MI.getOperand(OpNum), Fixups, STI);
uint64_t Len = getMachineOpValue(MI, MI.getOperand(OpNum + 2), Fixups) - 1; uint64_t Disp = getMachineOpValue(MI, MI.getOperand(OpNum + 1), Fixups, STI);
uint64_t Len = getMachineOpValue(MI, MI.getOperand(OpNum + 2), Fixups, STI) - 1;
assert(isUInt<4>(Base) && isUInt<12>(Disp) && isUInt<8>(Len)); assert(isUInt<4>(Base) && isUInt<12>(Disp) && isUInt<8>(Len));
return (Len << 16) | (Base << 12) | Disp; return (Len << 16) | (Base << 12) | Disp;
} }

15
utils/TableGen/CodeEmitterGen.cpp
View File

@ -122,14 +122,14 @@ AddCodeToMergeInOperand(Record *R, BitsInit *BI, const std::string &VarName,
Case += " // op: " + VarName + "\n" + Case += " // op: " + VarName + "\n" +
" op = " + EncoderMethodName + "(MI, " + utostr(OpIdx); " op = " + EncoderMethodName + "(MI, " + utostr(OpIdx);
if (MCEmitter) if (MCEmitter)
Case += ", Fixups"; Case += ", Fixups, STI";
Case += ");\n"; Case += ");\n";
} }
} else { } else {
Case += " // op: " + VarName + "\n" + Case += " // op: " + VarName + "\n" +
" op = getMachineOpValue(MI, MI.getOperand(" + utostr(OpIdx) + ")"; " op = getMachineOpValue(MI, MI.getOperand(" + utostr(OpIdx) + ")";
if (MCEmitter) if (MCEmitter)
Case += ", Fixups"; Case += ", Fixups, STI";
Case += ");\n"; Case += ");\n";
} }
@ -192,8 +192,12 @@ std::string CodeEmitterGen::getInstructionCase(Record *R,
} }
std::string PostEmitter = R->getValueAsString("PostEncoderMethod"); std::string PostEmitter = R->getValueAsString("PostEncoderMethod");
if (!PostEmitter.empty()) if (!PostEmitter.empty()) {
Case += " Value = " + PostEmitter + "(MI, Value);\n"; Case += " Value = " + PostEmitter + "(MI, Value";
if (MCEmitter)
Case += ", STI";
Case += ");\n";
}
return Case; return Case;
} }
@ -212,7 +216,8 @@ void CodeEmitterGen::run(raw_ostream &o) {
o << "uint64_t " << Target.getName(); o << "uint64_t " << Target.getName();
if (MCEmitter) if (MCEmitter)
o << "MCCodeEmitter::getBinaryCodeForInstr(const MCInst &MI,\n" o << "MCCodeEmitter::getBinaryCodeForInstr(const MCInst &MI,\n"
<< " SmallVectorImpl<MCFixup> &Fixups) const {\n"; << " SmallVectorImpl<MCFixup> &Fixups,\n"
<< " const MCSubtargetInfo &STI) const {\n";
else else
o << "CodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) const {\n"; o << "CodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) const {\n";