Remove NumberHack entirely.

SubRegIndex instances are now numbered uniquely the same way Register instances
are - in lexicographical order by name.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104627 91177308-0d34-0410-b5e6-96231b3b80d8

include/llvm/Target/Target.td

@@ -21,13 +21,9 @@ include "llvm/Intrinsics.td"
 
 class RegisterClass; // Forward def
 
-// SubRegIndex - Use instances on SubRegIndex to identify subregisters.
+// SubRegIndex - Use instances of SubRegIndex to identify subregisters.
 class SubRegIndex {
   string Namespace = "";
-
-  // This explicit numbering is going away after RegisterClass::SubRegClassList
-  // is replaced.
-  int NumberHack;
 }
 
 // Register - You should define one instance of this class for each register

lib/Target/ARM/ARMRegisterInfo.td

@@ -26,27 +26,27 @@ class ARMFReg<bits<6> num, string n> : Register<n> {
 // Subregister indices.
 let Namespace = "ARM" in {
 // Note: Code depends on these having consecutive numbers.
-def ssub_0 : SubRegIndex { let NumberHack = 1; }
-def ssub_1 : SubRegIndex { let NumberHack = 2; }
-def ssub_2 : SubRegIndex { let NumberHack = 3; }
-def ssub_3 : SubRegIndex { let NumberHack = 4; }
+def ssub_0 : SubRegIndex;
+def ssub_1 : SubRegIndex;
+def ssub_2 : SubRegIndex;
+def ssub_3 : SubRegIndex;
 
-def dsub_0 : SubRegIndex { let NumberHack = 5; }
-def dsub_1 : SubRegIndex { let NumberHack = 6; }
-def dsub_2 : SubRegIndex { let NumberHack = 7; }
-def dsub_3 : SubRegIndex { let NumberHack = 8; }
-def dsub_4 : SubRegIndex { let NumberHack = 9; }
-def dsub_5 : SubRegIndex { let NumberHack = 10; }
-def dsub_6 : SubRegIndex { let NumberHack = 11; }
-def dsub_7 : SubRegIndex { let NumberHack = 12; }
+def dsub_0 : SubRegIndex;
+def dsub_1 : SubRegIndex;
+def dsub_2 : SubRegIndex;
+def dsub_3 : SubRegIndex;
+def dsub_4 : SubRegIndex;
+def dsub_5 : SubRegIndex;
+def dsub_6 : SubRegIndex;
+def dsub_7 : SubRegIndex;
 
-def qsub_0 : SubRegIndex { let NumberHack = 13; }
-def qsub_1 : SubRegIndex { let NumberHack = 14; }
-def qsub_2 : SubRegIndex { let NumberHack = 15; }
-def qsub_3 : SubRegIndex { let NumberHack = 16; }
+def qsub_0 : SubRegIndex;
+def qsub_1 : SubRegIndex;
+def qsub_2 : SubRegIndex;
+def qsub_3 : SubRegIndex;
 
-def qqsub_0 : SubRegIndex { let NumberHack = 17; }
-def qqsub_1 : SubRegIndex { let NumberHack = 18; }
+def qqsub_0 : SubRegIndex;
+def qqsub_1 : SubRegIndex;
 }
 
 // Integer registers

lib/Target/Blackfin/BlackfinRegisterInfo.td

@@ -16,9 +16,9 @@
 // 2: .H
 // 3: .W (32 low bits of 40-bit accu)
 let Namespace = "BF" in {
-def lo16 : SubRegIndex { let NumberHack = 1; }
-def hi16 : SubRegIndex { let NumberHack = 2; }
-def lo32 : SubRegIndex { let NumberHack = 3; }
+def lo16 : SubRegIndex;
+def hi16 : SubRegIndex;
+def lo32 : SubRegIndex;
 }
 
 // Registers are identified with 3-bit group and 3-bit ID numbers.

lib/Target/MSP430/MSP430RegisterInfo.td

@@ -60,10 +60,7 @@ def R13W : MSP430RegWithSubregs<13, "r13", [R13B]>;
 def R14W : MSP430RegWithSubregs<14, "r14", [R14B]>;
 def R15W : MSP430RegWithSubregs<15, "r15", [R15B]>;
 
-def subreg_8bit : SubRegIndex {
-  let NumberHack = 1;
-  let Namespace = "MSP430";
-}
+def subreg_8bit : SubRegIndex { let Namespace = "MSP430"; }
 
 def : SubRegSet<subreg_8bit, [PCW, SPW, SRW, CGW, FPW, R5W, R6W, R7W,
                               R8W, R9W, R10W, R11W, R12W, R13W, R14W, R15W],

lib/Target/Mips/MipsRegisterInfo.td

@@ -145,8 +145,8 @@ let Namespace = "Mips" in {
 //===----------------------------------------------------------------------===//
 
 let Namespace = "Mips" in {
-def sub_fpeven : SubRegIndex { let NumberHack = 1; }
-def sub_fpodd  : SubRegIndex { let NumberHack = 2; }
+def sub_fpeven : SubRegIndex;
+def sub_fpodd  : SubRegIndex;
 }
 
 def : SubRegSet<sub_fpeven, [D0, D1, D2, D3, D4, D5, D6, D7,

lib/Target/PowerPC/PPCRegisterInfo.td

@@ -235,10 +235,10 @@ def CR6 : CR<6, "cr6", [CR6LT, CR6GT, CR6EQ, CR6UN]>, DwarfRegNum<[74]>;
 def CR7 : CR<7, "cr7", [CR7LT, CR7GT, CR7EQ, CR7UN]>, DwarfRegNum<[75]>;
 
 let Namespace = "PPC" in {
-def sub_lt : SubRegIndex { let NumberHack = 1; }
-def sub_gt : SubRegIndex { let NumberHack = 2; }
-def sub_eq : SubRegIndex { let NumberHack = 3; }
-def sub_un : SubRegIndex { let NumberHack = 4; }
+def sub_lt : SubRegIndex;
+def sub_gt : SubRegIndex;
+def sub_eq : SubRegIndex;
+def sub_un : SubRegIndex;
 }
 
 def : SubRegSet<sub_lt,

lib/Target/SystemZ/SystemZRegisterInfo.td

@@ -146,11 +146,11 @@ def F15L : FPRL<15, "f15", [F15S]>, DwarfRegNum<[31]>;
 def PSW : SystemZReg<"psw">;
 
 let Namespace = "SystemZ" in {
-def subreg_32bit  : SubRegIndex { let NumberHack = 1; }
-def subreg_even32 : SubRegIndex { let NumberHack = 1; }
-def subreg_odd32  : SubRegIndex { let NumberHack = 2; }
-def subreg_even   : SubRegIndex { let NumberHack = 3; }
-def subreg_odd    : SubRegIndex { let NumberHack = 4; }
+def subreg_32bit  : SubRegIndex;
+def subreg_even32 : SubRegIndex;
+def subreg_odd32  : SubRegIndex;
+def subreg_even   : SubRegIndex;
+def subreg_odd    : SubRegIndex;
 }
 
 def : SubRegSet<subreg_32bit, [R0D, R1D,  R2D,  R3D,  R4D,  R5D,  R6D,  R7D,

lib/Target/X86/X86RegisterInfo.td

@@ -19,14 +19,14 @@
 let Namespace = "X86" in {
 
   // Subregister indices.
-  def sub_8bit    : SubRegIndex { let NumberHack = 1; }
-  def sub_8bit_hi : SubRegIndex { let NumberHack = 2; }
-  def sub_16bit   : SubRegIndex { let NumberHack = 3; }
-  def sub_32bit   : SubRegIndex { let NumberHack = 4; }
+  def sub_8bit    : SubRegIndex;
+  def sub_8bit_hi : SubRegIndex;
+  def sub_16bit   : SubRegIndex;
+  def sub_32bit   : SubRegIndex;
 
-  def sub_ss  : SubRegIndex { let NumberHack = 1; }
-  def sub_sd  : SubRegIndex { let NumberHack = 2; }
-  def sub_xmm : SubRegIndex { let NumberHack = 3; }
+  def sub_ss  : SubRegIndex;
+  def sub_sd  : SubRegIndex;
+  def sub_xmm : SubRegIndex;
 
 
   // In the register alias definitions below, we define which registers alias