Add X86 MULX instruction for disassembler.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142738 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/X86/X86InstrArithmetic.td

@@ -1171,3 +1171,27 @@ let Predicates = [HasBMI], Defs = [EFLAGS] in {
   defm ANDN32 : bmi_andn<"andn{l}", GR32, i32mem, loadi32>, T8, VEX_4V;
   defm ANDN64 : bmi_andn<"andn{q}", GR64, i64mem, loadi64>, T8, VEX_4V, VEX_W;
 }
+
+//===----------------------------------------------------------------------===//
+// MULX Instruction
+//
+multiclass bmi_mulx<string mnemonic, RegisterClass RC, X86MemOperand x86memop> {
+let neverHasSideEffects = 1 in {
+  let isCommutable = 1 in
+  def rr : I<0xF6, MRMSrcReg, (outs RC:$dst1, RC:$dst2), (ins RC:$src),
+             !strconcat(mnemonic, "\t{$src, $dst2, $dst1|$dst1, $dst2, $src}"),
+             []>, T8XD, VEX_4V;
+
+  let mayLoad = 1 in
+  def rm : I<0xF6, MRMSrcMem, (outs RC:$dst1, RC:$dst2), (ins x86memop:$src),
+             !strconcat(mnemonic, "\t{$src, $dst2, $dst1|$dst1, $dst2, $src}"),
+             []>, T8XD, VEX_4V;
+}
+}
+
+let Predicates = [HasBMI2] in {
+  let Uses = [EDX] in
+    defm MULX32 : bmi_mulx<"mulx{l}", GR32, i32mem>;
+  let Uses = [RDX] in
+    defm MULX64 : bmi_mulx<"mulx{q}", GR64, i64mem>, VEX_W;
+}

test/MC/Disassembler/X86/simple-tests.txt

@@ -587,3 +587,15 @@
 
 # CHECK: pdepq (%rax), %r11, %r10
 0xc4 0x62 0xa3 0xf5 0x10
+
+# CHECK: mulxl %r12d, %r11d, %r10d
+0xc4 0x42 0x23 0xf6 0xd4
+
+# CHECK: mulxl (%rax), %r11d, %r10d
+0xc4 0x62 0x23 0xf6 0x10
+
+# CHECK: mulxq %r12, %r11, %r10
+0xc4 0x42 0xa3 0xf6 0xd4
+
+# CHECK: mulxq (%rax), %r11, %r10
+0xc4 0x62 0xa3 0xf6 0x10

test/MC/Disassembler/X86/x86-32.txt

@@ -531,3 +531,15 @@
 
 # CHECK: pdepl (%eax), %ecx, %edx
 0xc4 0xe2 0x73 0xf5 0x10
+
+# CHECK: mulxl %esp, %ecx, %edx
+0xc4 0xe2 0x73 0xf6 0xd4
+
+# CHECK: mulxl (%eax), %ecx, %edx
+0xc4 0xe2 0x73 0xf6 0x10
+
+# CHECK: mulxl %esp, %ecx, %edx
+0xc4 0xe2 0xf3 0xf6 0xd4
+
+# CHECK: mulxl (%eax), %ecx, %edx
+0xc4 0xe2 0xf3 0xf6 0x10