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avoid type mismatch when building SCEVs
This is a corner case I have stumbled upon when dealing with ARM64 type conversions. I was not able to extract a testcase for the community codebase to fail on. The patch conservatively discards a division that would have ended up in an ICE due to a type mismatch when building a multiply expression. I have also added code to a place that builds add expressions and in which we should be careful not to pass in operands of different types. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209694 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -7131,9 +7131,19 @@ public:
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void visitAddExpr(const SCEVAddExpr *Numerator) {
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SmallVector<const SCEV *, 2> Qs, Rs;
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Type *Ty = Denominator->getType();
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for (const SCEV *Op : Numerator->operands()) {
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const SCEV *Q, *R;
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divide(SE, Op, Denominator, &Q, &R);
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// Bail out if types do not match.
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if (Ty != Q->getType() || Ty != R->getType()) {
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Quotient = Zero;
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Remainder = Numerator;
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return;
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}
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Qs.push_back(Q);
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Rs.push_back(R);
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}
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@ -7150,9 +7160,17 @@ public:
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void visitMulExpr(const SCEVMulExpr *Numerator) {
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SmallVector<const SCEV *, 2> Qs;
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Type *Ty = Denominator->getType();
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bool FoundDenominatorTerm = false;
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for (const SCEV *Op : Numerator->operands()) {
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// Bail out if types do not match.
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if (Ty != Op->getType()) {
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Quotient = Zero;
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Remainder = Numerator;
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return;
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}
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if (FoundDenominatorTerm) {
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Qs.push_back(Op);
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continue;
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@ -7165,6 +7183,14 @@ public:
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Qs.push_back(Op);
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continue;
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}
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// Bail out if types do not match.
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if (Ty != Q->getType()) {
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Quotient = Zero;
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Remainder = Numerator;
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return;
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}
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FoundDenominatorTerm = true;
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Qs.push_back(Q);
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}
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