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https://github.com/c64scene-ar/llvm-6502.git
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Skip over deleted val#'s.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43700 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng
parent
5942efb0e5
commit
5031fd2d32
@ -805,7 +805,7 @@ bool SimpleRegisterCoalescing::JoinIntervals(LiveInterval &LHS,
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i != e; ++i) {
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VNInfo *VNI = *i;
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unsigned ValSrcReg = VNI->reg;
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if (ValSrcReg == 0) // Src not defined by a copy?
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if (VNI->def == ~1U ||ValSrcReg == 0) // Src not defined by a copy?
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continue;
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// DstReg is known to be a register in the LHS interval. If the src is
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@ -823,7 +823,7 @@ bool SimpleRegisterCoalescing::JoinIntervals(LiveInterval &LHS,
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i != e; ++i) {
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VNInfo *VNI = *i;
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unsigned ValSrcReg = VNI->reg;
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if (ValSrcReg == 0) // Src not defined by a copy?
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if (VNI->def == ~1U || ValSrcReg == 0) // Src not defined by a copy?
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continue;
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// DstReg is known to be a register in the RHS interval. If the src is
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148
test/CodeGen/PowerPC/2007-11-04-CoalescerCrash.ll
Normal file
148
test/CodeGen/PowerPC/2007-11-04-CoalescerCrash.ll
Normal file
@ -0,0 +1,148 @@
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; RUN: llvm-as < %s | llc -mtriple=powerpc-apple-darwin
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%struct.HDescriptor = type <{ i32, i32 }>
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declare void @bcopy(i8*, i8*, i32)
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define i32 @main(i32 %argc, i8** %argv) {
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entry:
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br i1 false, label %bb31, label %bb
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bb: ; preds = %entry
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ret i32 -6
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bb31: ; preds = %entry
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switch i32 0, label %bb189 [
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i32 73, label %cond_next209
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i32 74, label %bb74
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i32 77, label %bb57
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i32 78, label %cond_next209
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i32 85, label %cond_next209
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i32 97, label %cond_next209
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i32 100, label %cond_next209
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i32 107, label %cond_next209
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i32 109, label %bb57
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i32 112, label %bb43
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i32 115, label %cond_next209
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i32 117, label %bb51
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]
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bb43: ; preds = %bb31
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br i1 false, label %cond_true48, label %cond_true200.critedge2117
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cond_true48: ; preds = %bb43
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br i1 false, label %cond_next372, label %AllDone
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bb51: ; preds = %bb31
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ret i32 0
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bb57: ; preds = %bb31, %bb31
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ret i32 0
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bb74: ; preds = %bb31
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ret i32 0
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bb189: ; preds = %bb31
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ret i32 0
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cond_true200.critedge2117: ; preds = %bb43
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ret i32 0
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cond_next209: ; preds = %bb31, %bb31, %bb31, %bb31, %bb31, %bb31, %bb31
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ret i32 0
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cond_next372: ; preds = %cond_true48
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switch i32 0, label %bb1728 [
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i32 73, label %bb1723
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i32 74, label %cond_true1700
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i32 78, label %bb1718
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i32 85, label %bb1713
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i32 97, label %bb1620
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i32 107, label %AllDone
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i32 112, label %cond_next423
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i32 117, label %cond_next1453
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]
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cond_next423: ; preds = %cond_next372
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switch i16 0, label %cond_next691 [
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i16 18475, label %cond_next807
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i16 18520, label %cond_next807
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]
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cond_next691: ; preds = %cond_next423
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ret i32 0
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cond_next807: ; preds = %cond_next423, %cond_next423
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switch i16 0, label %cond_true1192 [
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i16 18475, label %cond_next21.i
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i16 18520, label %cond_next21.i
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]
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cond_next21.i: ; preds = %cond_next807, %cond_next807
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br i1 false, label %cond_next934, label %free.i
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free.i: ; preds = %cond_next21.i
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ret i32 0
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cond_next934: ; preds = %bb1005, %cond_next21.i
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%listsize.1 = phi i32 [ 0, %bb1005 ], [ 64, %cond_next21.i ] ; <i32> [#uses=1]
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%catalogExtents.2 = phi %struct.HDescriptor* [ %catalogExtents.1.reg2mem.1, %bb1005 ], [ null, %cond_next21.i ] ; <%struct.HDescriptor*> [#uses=3]
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br i1 false, label %cond_next942, label %Return1020
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cond_next942: ; preds = %cond_next934
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br i1 false, label %bb1005, label %bb947
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bb947: ; preds = %cond_next971, %cond_next942
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%indvar = phi i32 [ 0, %cond_next942 ], [ %indvar.next2140, %cond_next971 ] ; <i32> [#uses=2]
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%catalogExtents.1.reg2mem.0 = phi %struct.HDescriptor* [ %catalogExtents.2, %cond_next942 ], [ %tmp977978, %cond_next971 ] ; <%struct.HDescriptor*> [#uses=1]
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%extents.0.reg2mem.0 = phi %struct.HDescriptor* [ null, %cond_next942 ], [ %tmp977978, %cond_next971 ] ; <%struct.HDescriptor*> [#uses=1]
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br i1 false, label %cond_next971, label %Return1020
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cond_next971: ; preds = %bb947
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%tmp = shl i32 %indvar, 6 ; <i32> [#uses=1]
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%listsize.0.reg2mem.0 = add i32 %tmp, %listsize.1 ; <i32> [#uses=1]
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%tmp973 = add i32 %listsize.0.reg2mem.0, 64 ; <i32> [#uses=1]
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%tmp974975 = bitcast %struct.HDescriptor* %extents.0.reg2mem.0 to i8* ; <i8*> [#uses=1]
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%tmp977 = call i8* @realloc( i8* %tmp974975, i32 %tmp973 ) ; <i8*> [#uses=1]
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%tmp977978 = bitcast i8* %tmp977 to %struct.HDescriptor* ; <%struct.HDescriptor*> [#uses=3]
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call void @bcopy( i8* null, i8* null, i32 64 )
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%indvar.next2140 = add i32 %indvar, 1 ; <i32> [#uses=1]
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br i1 false, label %bb1005, label %bb947
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bb1005: ; preds = %cond_next971, %cond_next942
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%catalogExtents.1.reg2mem.1 = phi %struct.HDescriptor* [ %catalogExtents.2, %cond_next942 ], [ %tmp977978, %cond_next971 ] ; <%struct.HDescriptor*> [#uses=2]
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br i1 false, label %Return1020, label %cond_next934
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Return1020: ; preds = %bb1005, %bb947, %cond_next934
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%catalogExtents.3 = phi %struct.HDescriptor* [ %catalogExtents.1.reg2mem.0, %bb947 ], [ %catalogExtents.2, %cond_next934 ], [ %catalogExtents.1.reg2mem.1, %bb1005 ] ; <%struct.HDescriptor*> [#uses=0]
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ret i32 0
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cond_true1192: ; preds = %cond_next807
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ret i32 0
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cond_next1453: ; preds = %cond_next372
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ret i32 0
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bb1620: ; preds = %cond_next372
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ret i32 0
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cond_true1700: ; preds = %cond_next372
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ret i32 0
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bb1713: ; preds = %cond_next372
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ret i32 0
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bb1718: ; preds = %cond_next372
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ret i32 0
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bb1723: ; preds = %cond_next372
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ret i32 0
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bb1728: ; preds = %cond_next372
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ret i32 -6
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AllDone: ; preds = %cond_next372, %cond_true48
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ret i32 0
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}
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declare i8* @realloc(i8*, i32)
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