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Expand pseudos/macros for Selt. This is the last of the complex
macros.The rest is some small misc. stuff. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175950 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Reed Kotler
parent
1e8ed2537b
commit
50354a3f4a
@ -416,6 +416,7 @@ class SelT<string op1, string op2>:
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!strconcat(op1, "\t.+4\n\tmove $rd, $rs"))), []> {
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let isCodeGenOnly=1;
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let Constraints = "$rd = $rd_";
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let usesCustomInserter = 1;
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}
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//
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@ -1298,6 +1298,72 @@ MachineBasicBlock *MipsTargetLowering::EmitSel16(unsigned Opc, MachineInstr *MI,
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return BB;
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}
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MachineBasicBlock *MipsTargetLowering::EmitSelT16
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(unsigned Opc1, unsigned Opc2,
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MachineInstr *MI, MachineBasicBlock *BB) const {
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if (DontExpandCondPseudos16)
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return BB;
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const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
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DebugLoc dl = MI->getDebugLoc();
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// To "insert" a SELECT_CC instruction, we actually have to insert the
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// diamond control-flow pattern. The incoming instruction knows the
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// destination vreg to set, the condition code register to branch on, the
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// true/false values to select between, and a branch opcode to use.
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const BasicBlock *LLVM_BB = BB->getBasicBlock();
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MachineFunction::iterator It = BB;
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++It;
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// thisMBB:
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// ...
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// TrueVal = ...
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// setcc r1, r2, r3
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// bNE r1, r0, copy1MBB
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// fallthrough --> copy0MBB
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MachineBasicBlock *thisMBB = BB;
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MachineFunction *F = BB->getParent();
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MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
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MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
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F->insert(It, copy0MBB);
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F->insert(It, sinkMBB);
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// Transfer the remainder of BB and its successor edges to sinkMBB.
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sinkMBB->splice(sinkMBB->begin(), BB,
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llvm::next(MachineBasicBlock::iterator(MI)),
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BB->end());
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sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
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// Next, add the true and fallthrough blocks as its successors.
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BB->addSuccessor(copy0MBB);
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BB->addSuccessor(sinkMBB);
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BuildMI(BB, dl, TII->get(Opc2)).addReg(MI->getOperand(3).getReg())
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.addReg(MI->getOperand(4).getReg());
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BuildMI(BB, dl, TII->get(Opc1)).addMBB(sinkMBB);
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// copy0MBB:
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// %FalseValue = ...
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// # fallthrough to sinkMBB
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BB = copy0MBB;
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// Update machine-CFG edges
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BB->addSuccessor(sinkMBB);
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// sinkMBB:
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// %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ]
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// ...
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BB = sinkMBB;
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BuildMI(*BB, BB->begin(), dl,
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TII->get(Mips::PHI), MI->getOperand(0).getReg())
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.addReg(MI->getOperand(1).getReg()).addMBB(thisMBB)
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.addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB);
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MI->eraseFromParent(); // The pseudo instruction is gone now.
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return BB;
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}
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MachineBasicBlock *MipsTargetLowering::EmitSeliT16
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(unsigned Opc1, unsigned Opc2,
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MachineInstr *MI, MachineBasicBlock *BB) const {
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@ -1490,6 +1556,18 @@ MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
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return EmitSeliT16(Mips::BtnezX16, Mips::SltiRxImmX16, MI, BB);
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case Mips::SelTBtneZSltiu:
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return EmitSeliT16(Mips::BtnezX16, Mips::SltiuRxImmX16, MI, BB);
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case Mips::SelTBteqZCmp:
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return EmitSelT16(Mips::BteqzX16, Mips::CmpRxRy16, MI, BB);
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case Mips::SelTBteqZSlt:
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return EmitSelT16(Mips::BteqzX16, Mips::SltRxRy16, MI, BB);
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case Mips::SelTBteqZSltu:
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return EmitSelT16(Mips::BteqzX16, Mips::SltuRxRy16, MI, BB);
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case Mips::SelTBtneZCmp:
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return EmitSelT16(Mips::BtnezX16, Mips::CmpRxRy16, MI, BB);
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case Mips::SelTBtneZSlt:
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return EmitSelT16(Mips::BtnezX16, Mips::SltRxRy16, MI, BB);
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case Mips::SelTBtneZSltu:
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return EmitSelT16(Mips::BtnezX16, Mips::SltuRxRy16, MI, BB);
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}
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}
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@ -410,6 +410,9 @@ namespace llvm {
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MachineInstr *MI,
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MachineBasicBlock *BB) const;
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MachineBasicBlock *EmitSelT16(unsigned Opc1, unsigned Opc2,
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MachineInstr *MI,
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MachineBasicBlock *BB) const;
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};
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}
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@ -14,4 +14,5 @@ bosco: ; preds = %bosco, %entry
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; CHECK-PIC: b $BB0_1
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; CHECK-STATIC: j $BB0_1
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; CHECK-PIC16: b $BB0_1
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; CHECK-STATIC16: b $BB0_1
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; CHECK-STATIC16: b $BB0_1
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@ -20,7 +20,7 @@ entry:
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%cond = select i1 %cmp, i32 %2, i32 %3
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store i32 %cond, i32* @z1, align 4
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; 16: cmp ${{[0-9]+}}, ${{[0-9]+}}
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; 16: bteqz .+4
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; 16: bteqz $BB{{[0-9]+}}_{{[0-9]}}
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; 16: move ${{[0-9]+}}, ${{[0-9]+}}
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store i32 %cond, i32* @z2, align 4
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%4 = load i32* @c, align 4
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@ -91,7 +91,7 @@ entry:
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%cond = select i1 %cmp, i32 %2, i32 %3
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store i32 %cond, i32* @z1, align 4
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; 16: slt ${{[0-9]+}}, ${{[0-9]+}}
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; 16: bteqz .+4
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; 16: bteqz $BB{{[0-9]+}}_{{[0-9]}}
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; 16: move ${{[0-9]+}}, ${{[0-9]+}}
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%cmp1 = icmp sge i32 %1, %0
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%cond5 = select i1 %cmp1, i32 %3, i32 %2
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@ -112,7 +112,7 @@ entry:
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%1 = load i32* @b, align 4
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%cmp = icmp sgt i32 %0, %1
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; 16: slt ${{[0-9]+}}, ${{[0-9]+}}
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; 16: btnez .+4
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; 16: btnez $BB{{[0-9]+}}_{{[0-9]}}
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; 16: move ${{[0-9]+}}, ${{[0-9]+}}
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%2 = load i32* @f, align 4
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%3 = load i32* @t, align 4
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@ -141,7 +141,7 @@ entry:
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%cond = select i1 %cmp, i32 %2, i32 %3
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store i32 %cond, i32* @z1, align 4
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; 16: slt ${{[0-9]+}}, ${{[0-9]+}}
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; 16: bteqz .+4
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; 16: bteqz $BB{{[0-9]+}}_{{[0-9]}}
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; 16: move ${{[0-9]+}}, ${{[0-9]+}}
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%cmp1 = icmp sle i32 %1, %0
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%cond5 = select i1 %cmp1, i32 %3, i32 %2
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@ -165,7 +165,7 @@ entry:
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%cond = select i1 %cmp, i32 %1, i32 %2
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store i32 %cond, i32* @z1, align 4
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; 16: slti ${{[0-9]+}}, {{[0-9]+}}
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; 16: btnez .+4
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; 16: btnez $BB{{[0-9]+}}_{{[0-9]}}
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; 16: move ${{[0-9]+}}, ${{[0-9]+}}
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%3 = load i32* @b, align 4
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%cmp1 = icmp slt i32 %3, 2
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@ -192,7 +192,7 @@ entry:
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%cond = select i1 %cmp, i32 %2, i32 %3
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store i32 %cond, i32* @z1, align 4
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; 16: cmp ${{[0-9]+}}, ${{[0-9]+}}
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; 16: btnez .+4
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; 16: btnez $BB{{[0-9]+}}_{{[0-9]}}
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; 16: move ${{[0-9]+}}, ${{[0-9]+}}
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store i32 %cond, i32* @z2, align 4
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%4 = load i32* @c, align 4
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@ -284,7 +284,7 @@ entry:
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%cond = select i1 %cmp, i32 %2, i32 %3
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store i32 %cond, i32* @z1, align 4
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; 16: sltu ${{[0-9]+}}, ${{[0-9]+}}
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; 16: bteqz .+4
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; 16: bteqz $BB{{[0-9]+}}_{{[0-9]}}
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; 16: move ${{[0-9]+}}, ${{[0-9]+}}
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%cmp1 = icmp uge i32 %1, %0
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%cond5 = select i1 %cmp1, i32 %3, i32 %2
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@ -309,7 +309,7 @@ entry:
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%cond = select i1 %cmp, i32 %2, i32 %3
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store i32 %cond, i32* @z1, align 4
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; 16: sltu ${{[0-9]+}}, ${{[0-9]+}}
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; 16: btnez .+4
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; 16: btnez $BB{{[0-9]+}}_{{[0-9]}}
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; 16: move ${{[0-9]+}}, ${{[0-9]+}}
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%cmp1 = icmp ugt i32 %1, %0
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%cond5 = select i1 %cmp1, i32 %3, i32 %2
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@ -334,7 +334,7 @@ entry:
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%cond = select i1 %cmp, i32 %2, i32 %3
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store i32 %cond, i32* @z1, align 4
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; 16: sltu ${{[0-9]+}}, ${{[0-9]+}}
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; 16: bteqz .+4
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; 16: bteqz $BB{{[0-9]+}}_{{[0-9]}}
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; 16: move ${{[0-9]+}}, ${{[0-9]+}}
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%cmp1 = icmp ule i32 %1, %0
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%cond5 = select i1 %cmp1, i32 %3, i32 %2
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