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Add some very paranoid checking for operand/result reg class matchup
For instructions that define multiple results, use the right regclass to define the result, not always the rc of result #0 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23580 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -909,7 +909,7 @@ unsigned SimpleSched::CreateVirtualRegisters(MachineInstr *MI,
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MI->addRegOperand(ResultReg, MachineOperand::Def);
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for (unsigned i = 1; i != NumResults; ++i) {
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assert(OpInfo[i].RegClass && "Isn't a register operand!");
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MI->addRegOperand(RegMap->createVirtualRegister(OpInfo[0].RegClass),
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MI->addRegOperand(RegMap->createVirtualRegister(OpInfo[i].RegClass),
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MachineOperand::Def);
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}
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return ResultReg;
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@ -951,8 +951,17 @@ void SimpleSched::EmitNode(NodeInfo *NI) {
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assert(Node->getOperand(i).getValueType() != MVT::Other &&
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Node->getOperand(i).getValueType() != MVT::Flag &&
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"Chain and flag operands should occur at end of operand list!");
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// Get/emit the operand.
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unsigned VReg = getVR(Node->getOperand(i));
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MI->addRegOperand(VReg, MachineOperand::Use);
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MI->addRegOperand(getVR(Node->getOperand(i)), MachineOperand::Use);
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// Verify that it is right.
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assert(MRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?");
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assert(II.OpInfo[i+NumResults].RegClass &&
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"Don't have operand info for this instruction!");
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assert(RegMap->getRegClass(VReg) == II.OpInfo[i+NumResults].RegClass &&
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"Register class of operand and regclass of use don't agree!");
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} else if (ConstantSDNode *C =
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dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
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MI->addZeroExtImm64Operand(C->getValue());
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@ -979,7 +988,15 @@ void SimpleSched::EmitNode(NodeInfo *NI) {
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assert(Node->getOperand(i).getValueType() != MVT::Other &&
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Node->getOperand(i).getValueType() != MVT::Flag &&
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"Chain and flag operands should occur at end of operand list!");
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MI->addRegOperand(getVR(Node->getOperand(i)), MachineOperand::Use);
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unsigned VReg = getVR(Node->getOperand(i));
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MI->addRegOperand(VReg, MachineOperand::Use);
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// Verify that it is right.
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assert(MRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?");
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assert(II.OpInfo[i+NumResults].RegClass &&
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"Don't have operand info for this instruction!");
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assert(RegMap->getRegClass(VReg) == II.OpInfo[i+NumResults].RegClass &&
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"Register class of operand and regclass of use don't agree!");
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}
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}
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