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Fix decoding for indexed STRB and LDRB. Fixes <rdar://problem/9926161>.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137347 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Owen Anderson 2011-08-11 20:47:56 +00:00
parent bb688cec09
commit 508e1d3db5
2 changed files with 7 additions and 0 deletions
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4
lib/Target/ARM/Disassembler/ARMDisassembler.cpp
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@ -941,6 +941,8 @@ static bool DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn,
switch (Inst.getOpcode()) {
case ARM::STR_POST_IMM:
case ARM::STR_POST_REG:
case ARM::STRB_POST_IMM:
case ARM::STRB_POST_REG:
case ARM::STRTr:
case ARM::STRTi:
case ARM::STRBT_POST_REG:
@ -957,6 +959,8 @@ static bool DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn,
switch (Inst.getOpcode()) {
case ARM::LDR_POST_IMM:
case ARM::LDR_POST_REG:
case ARM::LDRB_POST_IMM:
case ARM::LDRB_POST_REG:
case ARM::LDR_PRE:
case ARM::LDRBT_POST_REG:
case ARM::LDRBT_POST_IMM:

3
test/MC/Disassembler/ARM/arm-tests.txt
View File

@ -305,3 +305,6 @@
# CHECK: andeq r0, r0, r0, lsr #32
0x20 0x00 0x00 0x00
# CHECK: strb r3, [r2], #1
0x01 0x30 0xc2 0xe4