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https://github.com/c64scene-ar/llvm-6502.git
synced 2024-11-01 15:11:24 +00:00
AVX-512: Added VRCP28 and VRSQRT28 instructions and intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192283 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Elena Demikhovsky
parent
d29bae8bc9
commit
50dc2ad46c
@ -2745,29 +2745,54 @@ let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
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def int_x86_avx512_sqrt_ps_512 : GCCBuiltin<"__builtin_ia32_sqrtps512">,
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Intrinsic<[llvm_v16f32_ty], [llvm_v16f32_ty], [IntrNoMem]>;
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def int_x86_avx512_rcp14_ps_512 : GCCBuiltin<"__builtin_ia32_avx512_rcp14ps512">,
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def int_x86_avx512_rcp14_ps_512 : GCCBuiltin<"__builtin_ia32_rcp14ps512">,
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Intrinsic<[llvm_v16f32_ty], [llvm_v16f32_ty],
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[IntrNoMem]>;
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def int_x86_avx512_rcp14_pd_512 : GCCBuiltin<"__builtin_ia32_avx512_rcp14pd512">,
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def int_x86_avx512_rcp14_pd_512 : GCCBuiltin<"__builtin_ia32_rcp14pd512">,
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Intrinsic<[llvm_v8f64_ty], [llvm_v8f64_ty],
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[IntrNoMem]>;
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def int_x86_avx512_rcp14_ss : GCCBuiltin<"__builtin_ia32_avx512_rcp14ss">,
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Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_v4f32_ty],
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def int_x86_avx512_rcp14_ss : GCCBuiltin<"__builtin_ia32_rcp14ss">,
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Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty],
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[IntrNoMem]>;
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def int_x86_avx512_rcp14_sd : GCCBuiltin<"__builtin_ia32_avx512_rcp14sd">,
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Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty, llvm_v2f64_ty],
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def int_x86_avx512_rcp14_sd : GCCBuiltin<"__builtin_ia32_rcp14sd">,
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Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty],
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[IntrNoMem]>;
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def int_x86_avx512_rsqrt14_ps_512 : GCCBuiltin<"__builtin_ia32_avx512_rsqrt14ps512">,
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def int_x86_avx512_rsqrt14_ps_512 : GCCBuiltin<"__builtin_ia32_rsqrt14ps512">,
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Intrinsic<[llvm_v16f32_ty], [llvm_v16f32_ty],
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[IntrNoMem]>;
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def int_x86_avx512_rsqrt14_pd_512 : GCCBuiltin<"__builtin_ia32_avx512_rsqrt14pd512">,
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def int_x86_avx512_rsqrt14_pd_512 : GCCBuiltin<"__builtin_ia32_rsqrt14pd512">,
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Intrinsic<[llvm_v8f64_ty], [llvm_v8f64_ty],
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[IntrNoMem]>;
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def int_x86_avx512_rsqrt14_ss : GCCBuiltin<"__builtin_ia32_avx512_rsqrt14ss">,
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Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_v4f32_ty],
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def int_x86_avx512_rsqrt14_ss : GCCBuiltin<"__builtin_ia32_rsqrt14ss">,
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Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty],
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[IntrNoMem]>;
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def int_x86_avx512_rsqrt14_sd : GCCBuiltin<"__builtin_ia32_avx512_rsqrt14sd">,
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Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty, llvm_v2f64_ty],
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def int_x86_avx512_rsqrt14_sd : GCCBuiltin<"__builtin_ia32_rsqrt14sd">,
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Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty],
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[IntrNoMem]>;
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def int_x86_avx512_rcp28_ps_512 : GCCBuiltin<"__builtin_ia32_rcp28ps512">,
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Intrinsic<[llvm_v16f32_ty], [llvm_v16f32_ty],
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[IntrNoMem]>;
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def int_x86_avx512_rcp28_pd_512 : GCCBuiltin<"__builtin_ia32_rcp28pd512">,
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Intrinsic<[llvm_v8f64_ty], [llvm_v8f64_ty],
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[IntrNoMem]>;
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def int_x86_avx512_rcp28_ss : GCCBuiltin<"__builtin_ia32_rcp28ss">,
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Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty],
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[IntrNoMem]>;
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def int_x86_avx512_rcp28_sd : GCCBuiltin<"__builtin_ia32_rcp28sd">,
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Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty],
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[IntrNoMem]>;
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def int_x86_avx512_rsqrt28_ps_512 : GCCBuiltin<"__builtin_ia32_rsqrt28ps512">,
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Intrinsic<[llvm_v16f32_ty], [llvm_v16f32_ty],
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[IntrNoMem]>;
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def int_x86_avx512_rsqrt28_pd_512 : GCCBuiltin<"__builtin_ia32_rsqrt28pd512">,
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Intrinsic<[llvm_v8f64_ty], [llvm_v8f64_ty],
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[IntrNoMem]>;
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def int_x86_avx512_rsqrt28_ss : GCCBuiltin<"__builtin_ia32_rsqrt28ss">,
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Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty],
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[IntrNoMem]>;
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def int_x86_avx512_rsqrt28_sd : GCCBuiltin<"__builtin_ia32_rsqrt28sd">,
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Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty],
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[IntrNoMem]>;
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}
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@ -2910,14 +2935,14 @@ let TargetPrefix = "x86" in {
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}
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let TargetPrefix = "x86" in {
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def int_x86_avx512_mskblend_ps_512 : GCCBuiltin<"__builtin_ia32_avx512_mskblendps512">,
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def int_x86_avx512_mskblend_ps_512 : GCCBuiltin<"__builtin_ia32_mskblendps512">,
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Intrinsic<[llvm_v16f32_ty],
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[llvm_i16_ty, llvm_v16f32_ty, llvm_v16f32_ty],
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[IntrNoMem]>;
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def int_x86_avx512_cmpeq_pi_512 : GCCBuiltin<"__builtin_ia32_avx512_cmpeqpi512">,
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def int_x86_avx512_cmpeq_pi_512 : GCCBuiltin<"__builtin_ia32_cmpeqpi512">,
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Intrinsic<[llvm_i16_ty], [llvm_v16i32_ty, llvm_v16i32_ty],
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[IntrNoMem]>;
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def int_x86_avx512_and_pi : GCCBuiltin<"__builtin_ia32_avx512_andpi512">,
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def int_x86_avx512_and_pi : GCCBuiltin<"__builtin_ia32_andpi512">,
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Intrinsic<[llvm_v16i32_ty], [llvm_v16i32_ty, llvm_v16i32_ty],
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[IntrNoMem]>;
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}
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@ -2643,8 +2643,7 @@ multiclass avx512_fp_unop_p_int<bits<8> opc, string OpcodeStr,
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}
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/// avx512_fp_unop_s - AVX-512 unops in scalar form.
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multiclass avx512_fp_unop_s<bits<8> opc, string OpcodeStr,
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Intrinsic F32Int, Intrinsic F64Int> {
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multiclass avx512_fp_unop_s<bits<8> opc, string OpcodeStr> {
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let hasSideEffects = 0 in {
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def SSZr : AVX5128I<opc, MRMSrcReg, (outs FR32X:$dst),
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(ins FR32X:$src1, FR32X:$src2),
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@ -2661,8 +2660,7 @@ multiclass avx512_fp_unop_s<bits<8> opc, string OpcodeStr,
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(ins VR128X:$src1, ssmem:$src2),
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!strconcat(OpcodeStr,
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"ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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[(set VR128X:$dst, (F32Int VR128X:$src1, sse_load_f32:$src2))]>,
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EVEX_4V, EVEX_CD8<32, CD8VT1>;
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[]>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
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}
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def SDZr : AVX5128I<opc, MRMSrcReg, (outs FR64X:$dst),
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(ins FR64X:$src1, FR64X:$src2),
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@ -2674,29 +2672,67 @@ multiclass avx512_fp_unop_s<bits<8> opc, string OpcodeStr,
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(ins FR64X:$src1, f64mem:$src2),
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!strconcat(OpcodeStr,
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"sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
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EVEX_4V, VEX_W, EVEX_CD8<32, CD8VT1>;
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EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
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def SDZm_Int : AVX5128I<opc, MRMSrcMem, (outs VR128X:$dst),
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(ins VR128X:$src1, sdmem:$src2),
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!strconcat(OpcodeStr,
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"sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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[(set VR128X:$dst, (F64Int VR128X:$src1, sse_load_f64:$src2))]>,
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EVEX_4V, VEX_W, EVEX_CD8<32, CD8VT1>;
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[]>, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
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}
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}
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}
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defm VRCP14 : avx512_fp_unop_s<0x4D, "vrcp14", int_x86_avx512_rcp14_ss,
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int_x86_avx512_rcp14_sd>,
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defm VRCP14 : avx512_fp_unop_s<0x4D, "vrcp14">,
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avx512_fp_unop_p<0x4C, "vrcp14", X86frcp>,
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avx512_fp_unop_p_int<0x4C, "vrcp14",
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int_x86_avx512_rcp14_ps_512, int_x86_avx512_rcp14_pd_512>;
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defm VRSQRT14 : avx512_fp_unop_s<0x4F, "vrsqrt14", int_x86_avx512_rsqrt14_ss,
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int_x86_avx512_rsqrt14_sd>,
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defm VRSQRT14 : avx512_fp_unop_s<0x4F, "vrsqrt14">,
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avx512_fp_unop_p<0x4E, "vrsqrt14", X86frsqrt>,
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avx512_fp_unop_p_int<0x4E, "vrsqrt14",
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int_x86_avx512_rsqrt14_ps_512, int_x86_avx512_rsqrt14_pd_512>;
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def : Pat<(int_x86_avx512_rsqrt14_ss VR128X:$src),
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(COPY_TO_REGCLASS (VRSQRT14SSZr (f32 (IMPLICIT_DEF)),
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(COPY_TO_REGCLASS VR128X:$src, FR32)),
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VR128X)>;
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def : Pat<(int_x86_avx512_rsqrt14_ss sse_load_f32:$src),
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(VRSQRT14SSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
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def : Pat<(int_x86_avx512_rcp14_ss VR128X:$src),
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(COPY_TO_REGCLASS (VRCP14SSZr (f32 (IMPLICIT_DEF)),
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(COPY_TO_REGCLASS VR128X:$src, FR32)),
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VR128X)>;
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def : Pat<(int_x86_avx512_rcp14_ss sse_load_f32:$src),
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(VRCP14SSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
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let AddedComplexity = 20, Predicates = [HasERI] in {
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defm VRCP28 : avx512_fp_unop_s<0xCB, "vrcp28">,
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avx512_fp_unop_p<0xCA, "vrcp28", X86frcp>,
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avx512_fp_unop_p_int<0xCA, "vrcp28",
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int_x86_avx512_rcp28_ps_512, int_x86_avx512_rcp28_pd_512>;
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defm VRSQRT28 : avx512_fp_unop_s<0xCD, "vrsqrt28">,
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avx512_fp_unop_p<0xCC, "vrsqrt28", X86frsqrt>,
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avx512_fp_unop_p_int<0xCC, "vrsqrt28",
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int_x86_avx512_rsqrt28_ps_512, int_x86_avx512_rsqrt28_pd_512>;
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}
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let Predicates = [HasERI] in {
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def : Pat<(int_x86_avx512_rsqrt28_ss VR128X:$src),
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(COPY_TO_REGCLASS (VRSQRT28SSZr (f32 (IMPLICIT_DEF)),
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(COPY_TO_REGCLASS VR128X:$src, FR32)),
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VR128X)>;
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def : Pat<(int_x86_avx512_rsqrt28_ss sse_load_f32:$src),
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(VRSQRT28SSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
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def : Pat<(int_x86_avx512_rcp28_ss VR128X:$src),
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(COPY_TO_REGCLASS (VRCP28SSZr (f32 (IMPLICIT_DEF)),
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(COPY_TO_REGCLASS VR128X:$src, FR32)),
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VR128X)>;
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def : Pat<(int_x86_avx512_rcp28_ss sse_load_f32:$src),
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(VRCP28SSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
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}
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multiclass avx512_sqrt_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
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Intrinsic V16F32Int, Intrinsic V8F64Int,
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OpndItins itins_s, OpndItins itins_d> {
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@ -2810,28 +2846,45 @@ defm VSQRT : avx512_sqrt_scalar<0x51, "sqrt",
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int_x86_avx512_sqrt_ps_512, int_x86_avx512_sqrt_pd_512,
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SSE_SQRTPS, SSE_SQRTPD>;
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def : Pat<(f32 (fsqrt FR32X:$src)),
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(VSQRTSSZr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
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def : Pat<(f32 (fsqrt (load addr:$src))),
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(VSQRTSSZm (f32 (IMPLICIT_DEF)), addr:$src)>,
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Requires<[OptForSize]>;
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def : Pat<(f64 (fsqrt FR64X:$src)),
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(VSQRTSDZr (f64 (IMPLICIT_DEF)), FR64X:$src)>;
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def : Pat<(f64 (fsqrt (load addr:$src))),
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(VSQRTSDZm (f64 (IMPLICIT_DEF)), addr:$src)>,
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Requires<[OptForSize]>;
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let Predicates = [HasAVX512] in {
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def : Pat<(f32 (fsqrt FR32X:$src)),
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(VSQRTSSZr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
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def : Pat<(f32 (fsqrt (load addr:$src))),
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(VSQRTSSZm (f32 (IMPLICIT_DEF)), addr:$src)>,
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Requires<[OptForSize]>;
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def : Pat<(f64 (fsqrt FR64X:$src)),
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(VSQRTSDZr (f64 (IMPLICIT_DEF)), FR64X:$src)>;
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def : Pat<(f64 (fsqrt (load addr:$src))),
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(VSQRTSDZm (f64 (IMPLICIT_DEF)), addr:$src)>,
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Requires<[OptForSize]>;
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def : Pat<(f32 (X86frsqrt FR32X:$src)),
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(VRSQRT14SSZr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
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def : Pat<(f32 (X86frsqrt (load addr:$src))),
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(VRSQRT14SSZm (f32 (IMPLICIT_DEF)), addr:$src)>,
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Requires<[OptForSize]>;
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def : Pat<(f32 (X86frsqrt FR32X:$src)),
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(VRSQRT14SSZr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
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def : Pat<(f32 (X86frsqrt (load addr:$src))),
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(VRSQRT14SSZm (f32 (IMPLICIT_DEF)), addr:$src)>,
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Requires<[OptForSize]>;
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def : Pat<(f32 (X86frcp FR32X:$src)),
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(VRCP14SSZr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
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def : Pat<(f32 (X86frcp (load addr:$src))),
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(VRCP14SSZm (f32 (IMPLICIT_DEF)), addr:$src)>,
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Requires<[OptForSize]>;
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def : Pat<(int_x86_sse_sqrt_ss VR128X:$src),
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(COPY_TO_REGCLASS (VSQRTSSZr (f32 (IMPLICIT_DEF)),
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(COPY_TO_REGCLASS VR128X:$src, FR32)),
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VR128X)>;
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def : Pat<(int_x86_sse_sqrt_ss sse_load_f32:$src),
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(VSQRTSSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
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def : Pat<(int_x86_sse2_sqrt_sd VR128X:$src),
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(COPY_TO_REGCLASS (VSQRTSDZr (f64 (IMPLICIT_DEF)),
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(COPY_TO_REGCLASS VR128X:$src, FR64)),
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VR128X)>;
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def : Pat<(int_x86_sse2_sqrt_sd sse_load_f64:$src),
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(VSQRTSDZm_Int (v2f64 (IMPLICIT_DEF)), sse_load_f64:$src)>;
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}
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def : Pat<(f32 (X86frcp FR32X:$src)),
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(VRCP14SSZr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
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def : Pat<(f32 (X86frcp (load addr:$src))),
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(VRCP14SSZm (f32 (IMPLICIT_DEF)), addr:$src)>,
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Requires<[OptForSize]>;
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multiclass avx512_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
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X86MemOperand x86memop, RegisterClass RC,
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@ -649,13 +649,13 @@ def HasSSE4A : Predicate<"Subtarget->hasSSE4A()">;
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def HasAVX : Predicate<"Subtarget->hasAVX()">;
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def HasAVX2 : Predicate<"Subtarget->hasAVX2()">;
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def HasAVX1Only : Predicate<"Subtarget->hasAVX() && !Subtarget->hasAVX2()">;
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def HasAVX512 : Predicate<"Subtarget->hasAVX512()">;
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def HasAVX512 : Predicate<"Subtarget->hasAVX512()">;
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def UseAVX : Predicate<"Subtarget->hasAVX() && !Subtarget->hasAVX512()">;
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def UseAVX2 : Predicate<"Subtarget->hasAVX2() && !Subtarget->hasAVX512()">;
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def NoAVX512 : Predicate<"!Subtarget->hasAVX512()">;
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def HasCDI : Predicate<"Subtarget->hasCDI()">;
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def HasPFI : Predicate<"Subtarget->hasPFI()">;
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def HasEMI : Predicate<"Subtarget->hasERI()">;
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def HasERI : Predicate<"Subtarget->hasERI()">;
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def HasPOPCNT : Predicate<"Subtarget->hasPOPCNT()">;
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def HasAES : Predicate<"Subtarget->hasAES()">;
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@ -3357,7 +3357,8 @@ let Predicates = [UseAVX] in {
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def : Pat<(f32 (X86frcp (load addr:$src))),
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(VRCPSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
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Requires<[HasAVX, OptForSize]>;
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}
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let Predicates = [UseAVX] in {
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def : Pat<(int_x86_sse_sqrt_ss VR128:$src),
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(COPY_TO_REGCLASS (VSQRTSSr (f32 (IMPLICIT_DEF)),
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(COPY_TO_REGCLASS VR128:$src, FR32)),
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@ -3371,7 +3372,9 @@ let Predicates = [UseAVX] in {
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VR128)>;
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def : Pat<(int_x86_sse2_sqrt_sd sse_load_f64:$src),
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(VSQRTSDm_Int (v2f64 (IMPLICIT_DEF)), sse_load_f64:$src)>;
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}
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let Predicates = [HasAVX] in {
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def : Pat<(int_x86_sse_rsqrt_ss VR128:$src),
|
||||
(COPY_TO_REGCLASS (VRSQRTSSr (f32 (IMPLICIT_DEF)),
|
||||
(COPY_TO_REGCLASS VR128:$src, FR32)),
|
||||
|
||||
@ -1,39 +1,52 @@
|
||||
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=knl | FileCheck %s
|
||||
|
||||
declare i32 @llvm.x86.avx512.kortestz(i16, i16) nounwind readnone
|
||||
; CHECK: test_x86_avx3_kortestz
|
||||
; CHECK: test_kortestz
|
||||
; CHECK: kortestw
|
||||
; CHECK: sete
|
||||
define i32 @test_x86_avx3_kortestz(i16 %a0, i16 %a1) {
|
||||
define i32 @test_kortestz(i16 %a0, i16 %a1) {
|
||||
%res = call i32 @llvm.x86.avx512.kortestz(i16 %a0, i16 %a1)
|
||||
ret i32 %res
|
||||
}
|
||||
|
||||
declare i32 @llvm.x86.avx512.kortestc(i16, i16) nounwind readnone
|
||||
; CHECK: test_x86_avx3_kortestc
|
||||
; CHECK: test_kortestc
|
||||
; CHECK: kortestw
|
||||
; CHECK: sbbl
|
||||
define i32 @test_x86_avx3_kortestc(i16 %a0, i16 %a1) {
|
||||
define i32 @test_kortestc(i16 %a0, i16 %a1) {
|
||||
%res = call i32 @llvm.x86.avx512.kortestc(i16 %a0, i16 %a1)
|
||||
ret i32 %res
|
||||
}
|
||||
|
||||
define <16 x float> @test_x86_avx3_rcp_ps_512(<16 x float> %a0) {
|
||||
define <16 x float> @test_rcp_ps_512(<16 x float> %a0) {
|
||||
; CHECK: vrcp14ps
|
||||
%res = call <16 x float> @llvm.x86.avx512.rcp14.ps.512(<16 x float> %a0) ; <<16 x float>> [#uses=1]
|
||||
ret <16 x float> %res
|
||||
}
|
||||
declare <16 x float> @llvm.x86.avx512.rcp14.ps.512(<16 x float>) nounwind readnone
|
||||
|
||||
define <8 x double> @test_x86_avx3_rcp_pd_512(<8 x double> %a0) {
|
||||
define <8 x double> @test_rcp_pd_512(<8 x double> %a0) {
|
||||
; CHECK: vrcp14pd
|
||||
%res = call <8 x double> @llvm.x86.avx512.rcp14.pd.512(<8 x double> %a0) ; <<8 x double>> [#uses=1]
|
||||
ret <8 x double> %res
|
||||
}
|
||||
declare <8 x double> @llvm.x86.avx512.rcp14.pd.512(<8 x double>) nounwind readnone
|
||||
|
||||
define <16 x float> @test_rcp28_ps_512(<16 x float> %a0) {
|
||||
; CHECK: vrcp28ps
|
||||
%res = call <16 x float> @llvm.x86.avx512.rcp28.ps.512(<16 x float> %a0) ; <<16 x float>> [#uses=1]
|
||||
ret <16 x float> %res
|
||||
}
|
||||
declare <16 x float> @llvm.x86.avx512.rcp28.ps.512(<16 x float>) nounwind readnone
|
||||
|
||||
define <8 x double> @test_x86_avx3_rndscale_pd_512(<8 x double> %a0) {
|
||||
define <8 x double> @test_rcp28_pd_512(<8 x double> %a0) {
|
||||
; CHECK: vrcp28pd
|
||||
%res = call <8 x double> @llvm.x86.avx512.rcp28.pd.512(<8 x double> %a0) ; <<8 x double>> [#uses=1]
|
||||
ret <8 x double> %res
|
||||
}
|
||||
declare <8 x double> @llvm.x86.avx512.rcp28.pd.512(<8 x double>) nounwind readnone
|
||||
|
||||
define <8 x double> @test_rndscale_pd_512(<8 x double> %a0) {
|
||||
; CHECK: vrndscale
|
||||
%res = call <8 x double> @llvm.x86.avx512.rndscale.pd.512(<8 x double> %a0, i32 7) ; <<8 x double>> [#uses=1]
|
||||
ret <8 x double> %res
|
||||
@ -41,7 +54,7 @@ define <8 x double> @test_x86_avx3_rndscale_pd_512(<8 x double> %a0) {
|
||||
declare <8 x double> @llvm.x86.avx512.rndscale.pd.512(<8 x double>, i32) nounwind readnone
|
||||
|
||||
|
||||
define <16 x float> @test_x86_avx3_rndscale_ps_512(<16 x float> %a0) {
|
||||
define <16 x float> @test_rndscale_ps_512(<16 x float> %a0) {
|
||||
; CHECK: vrndscale
|
||||
%res = call <16 x float> @llvm.x86.avx512.rndscale.ps.512(<16 x float> %a0, i32 7) ; <<16 x float>> [#uses=1]
|
||||
ret <16 x float> %res
|
||||
@ -49,37 +62,70 @@ define <16 x float> @test_x86_avx3_rndscale_ps_512(<16 x float> %a0) {
|
||||
declare <16 x float> @llvm.x86.avx512.rndscale.ps.512(<16 x float>, i32) nounwind readnone
|
||||
|
||||
|
||||
define <16 x float> @test_x86_avx3_rsqrt_ps_512(<16 x float> %a0) {
|
||||
define <16 x float> @test_rsqrt_ps_512(<16 x float> %a0) {
|
||||
; CHECK: vrsqrt14ps
|
||||
%res = call <16 x float> @llvm.x86.avx512.rsqrt14.ps.512(<16 x float> %a0) ; <<16 x float>> [#uses=1]
|
||||
ret <16 x float> %res
|
||||
}
|
||||
declare <16 x float> @llvm.x86.avx512.rsqrt14.ps.512(<16 x float>) nounwind readnone
|
||||
|
||||
define <16 x float> @test_rsqrt28_ps_512(<16 x float> %a0) {
|
||||
; CHECK: vrsqrt28ps
|
||||
%res = call <16 x float> @llvm.x86.avx512.rsqrt28.ps.512(<16 x float> %a0) ; <<16 x float>> [#uses=1]
|
||||
ret <16 x float> %res
|
||||
}
|
||||
declare <16 x float> @llvm.x86.avx512.rsqrt28.ps.512(<16 x float>) nounwind readnone
|
||||
|
||||
define <8 x double> @test_x86_avx3_sqrt_pd_512(<8 x double> %a0) {
|
||||
define <4 x float> @test_rsqrt14_ss(<4 x float> %a0) {
|
||||
; CHECK: vrsqrt14ss
|
||||
%res = call <4 x float> @llvm.x86.avx512.rsqrt14.ss(<4 x float> %a0) ; <<4 x float>> [#uses=1]
|
||||
ret <4 x float> %res
|
||||
}
|
||||
declare <4 x float> @llvm.x86.avx512.rsqrt14.ss(<4 x float>) nounwind readnone
|
||||
|
||||
define <4 x float> @test_rsqrt28_ss(<4 x float> %a0) {
|
||||
; CHECK: vrsqrt28ss
|
||||
%res = call <4 x float> @llvm.x86.avx512.rsqrt28.ss(<4 x float> %a0) ; <<4 x float>> [#uses=1]
|
||||
ret <4 x float> %res
|
||||
}
|
||||
declare <4 x float> @llvm.x86.avx512.rsqrt28.ss(<4 x float>) nounwind readnone
|
||||
|
||||
define <4 x float> @test_rcp14_ss(<4 x float> %a0) {
|
||||
; CHECK: vrcp14ss
|
||||
%res = call <4 x float> @llvm.x86.avx512.rcp14.ss(<4 x float> %a0) ; <<4 x float>> [#uses=1]
|
||||
ret <4 x float> %res
|
||||
}
|
||||
declare <4 x float> @llvm.x86.avx512.rcp14.ss(<4 x float>) nounwind readnone
|
||||
|
||||
define <4 x float> @test_rcp28_ss(<4 x float> %a0) {
|
||||
; CHECK: vrcp28ss
|
||||
%res = call <4 x float> @llvm.x86.avx512.rcp28.ss(<4 x float> %a0) ; <<4 x float>> [#uses=1]
|
||||
ret <4 x float> %res
|
||||
}
|
||||
declare <4 x float> @llvm.x86.avx512.rcp28.ss(<4 x float>) nounwind readnone
|
||||
|
||||
define <8 x double> @test_sqrt_pd_512(<8 x double> %a0) {
|
||||
; CHECK: vsqrtpd
|
||||
%res = call <8 x double> @llvm.x86.avx512.sqrt.pd.512(<8 x double> %a0) ; <<8 x double>> [#uses=1]
|
||||
ret <8 x double> %res
|
||||
}
|
||||
declare <8 x double> @llvm.x86.avx512.sqrt.pd.512(<8 x double>) nounwind readnone
|
||||
|
||||
|
||||
define <16 x float> @test_x86_avx3_sqrt_ps_512(<16 x float> %a0) {
|
||||
define <16 x float> @test_sqrt_ps_512(<16 x float> %a0) {
|
||||
; CHECK: vsqrtps
|
||||
%res = call <16 x float> @llvm.x86.avx512.sqrt.ps.512(<16 x float> %a0) ; <<16 x float>> [#uses=1]
|
||||
ret <16 x float> %res
|
||||
}
|
||||
declare <16 x float> @llvm.x86.avx512.sqrt.ps.512(<16 x float>) nounwind readnone
|
||||
|
||||
define <4 x float> @test_x86_avx3_sqrt_ss(<4 x float> %a0, <4 x float> %a1) {
|
||||
define <4 x float> @test_sqrt_ss(<4 x float> %a0, <4 x float> %a1) {
|
||||
; CHECK: vsqrtssz
|
||||
%res = call <4 x float> @llvm.x86.avx512.sqrt.ss(<4 x float> %a0, <4 x float> %a1) ; <<4 x float>> [#uses=1]
|
||||
ret <4 x float> %res
|
||||
}
|
||||
declare <4 x float> @llvm.x86.avx512.sqrt.ss(<4 x float>, <4 x float>) nounwind readnone
|
||||
|
||||
define <2 x double> @test_x86_avx3_sqrt_sd(<2 x double> %a0, <2 x double> %a1) {
|
||||
define <2 x double> @test_sqrt_sd(<2 x double> %a0, <2 x double> %a1) {
|
||||
; CHECK: vsqrtsdz
|
||||
%res = call <2 x double> @llvm.x86.avx512.sqrt.sd(<2 x double> %a0, <2 x double> %a1) ; <<2 x double>> [#uses=1]
|
||||
ret <2 x double> %res
|
||||
|
||||
Loading…
Reference in New Issue
Block a user